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參數(shù)資料
| 型號： | ISL6554CBZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Microprocessor CORE Voltage Regulator Using Multi-Phase Buck PWM Control Without Programmable Droop |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封裝： | PLASTIC, LEAD FREE, MS-013-AC, SOIC-20 |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 492K |
| 代理商： | ISL6554CBZ-T |
10
FN9003.3
February 11, 2005
time. PGOOD also goes “l(fā)ow” during this time due to VSEN
going below its threshold voltage. To lower the average
output dissipation, the soft-start initial wait time is increased
from 32 to 2048 cycles, then the soft-start ramp is initiated.
At a PWM frequency of 200kHz, for instance, an overcurrent
detection would cause a dead time of 10.24ms, then a ramp
of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
soft-start ramp is initiated. If a short is present at that time,
the cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to
the high short circuit current, overcurrent is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal soft-start cycle.
CORE Voltage Programming
The voltage identification pins (VID0, VID1,VID2,VID3 and
VID4) set the CORE output voltage. Each VID pin is pulled to
VCC by an internal 20
μ
A current source and accepts open-
collector/open-drain/open-switch-to-ground or standard low-
voltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is
±
1% accurate over
the operating temperature and voltage range.
Current Sensing and Balancing
Overview
The ISL6554 samples the on-state voltage drop across each
synchronous rectifier MOSFET, Q2, as an indication of the
inductor current in that phase (see Figure 7). Neglecting AC
effects (to be discussed later), the voltage drop across Q2 is
simply r
DS(ON)
(Q2) x
inductor current (I
L
). Note that I
L
, the
inductor current, is either 1/2, 1/3, or 1/4 of the total current
(I
LT
), depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
R
ISEN
resistor to develop the I
ISEN
current to the ISL6554
ISEN pin. This pin is held at virtual ground, so the current
through R
ISEN
is I
L
x
r
DS(ON)
(Q2) / R
ISEN
.
The I
ISEN
current provides information to perform the
following functions:
1. Detection of an overcurrent condition
2. Balance the I
L
currents in multiple channels
Overcurrent, Selecting RISEN
The current detected through the R
ISEN
resistor is
averaged with the current(s) detected in the other 1, 2, or 3
channels. The averaged current is compared with a
trimmed,
internally generated current, and used to detect
an overcurrent condition.
TABLE 1. VOLTAGE IDENTIFICATION CODES
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VID4
VID3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
VCC
CORE
(V
DC
)
Output Off
0.95
0.975
1.000
1.025
1.050
1.075
1.100
1.125
VID2
1
1
1
1
0
0
0
0
1
VID1
1
1
0
0
1
1
0
0
1
VID0
1
0
1
0
1
0
1
0
1
PGOOD
SHORT
50A/DIV.
CURRENT
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
SUPPLY FREQUENCY = 200kHz, V
IN
= 12V
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SHORT APPLIED HERE
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
1
0
1
0
1.600
1.625
1.650
1.675
1.700
TABLE 1. VOLTAGE IDENTIFICATION CODES (Continued)
VOLTAGE IDENTIFICATION CODE AT
PROCESSOR PINS
VCC
CORE
(V
DC
)
VID4
VID3
VID2
VID1
VID0
ISL6554
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