參數(shù)資料
型號: ISL6557ACBZ-T
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Multi-Phase PWM Controller for Core-Voltage Regulation
中文描述: SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO24
封裝: LEAD FREE, PLASTIC, MS-013AD, SOIC-24
文件頁數(shù): 12/19頁
文件大?。?/td> 540K
代理商: ISL6557ACBZ-T
12
During the soft-start interval, the soft-start voltage, V
RAM
P
,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I
RAMP
, is
decreasing from 160
μ
A down to zero. These signals are
connected as shown in Figure 9 (I
OUT
may or may not be
connected to FB depending on the particular application).
The ideal diodes in Figure 9 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V
RAM
P
. Since I
RAMP
creates an initial offset
across R
FB
of R
FB
times 160
μ
A, the first PWM pulses will
not be seen until V
RAMP
is greater than the R
F
B
I
RAMP
offset. This produces a delay after the ISL6557A enables
before the output voltage starts moving. For example, if
VID = 1.5V, R
FB
= 1k
and T
SS
= 8.3ms, the delay time
can be expressed using Equation 6.
From this point, the soft start ramps linearly until V
RAMP
reaches VID. For the system described above, this first linear
ramp will continue for approximately
The final portion of the soft-start sequence is the time
remaining after V
RAMP
reaches VID and before I
RAMP
gets to
zero. This is also characterized by a slight linear ramp in the
output voltage which, for the current example, exists for a time
This behavior is seen in the example in Figure 10 of a converter
switching at 500kHz. For this converter, R
FB
is set to 2.67k
leading to T
SS
= 4.0ms, t
DELAY
= 700ns, t
RAMP1
= 2.23ms,
and t
RAMP2
= 1.17ms.
NOTE: Switching frequency 500kHz and R
FB
= 2.67k
DYNAMIC VID
The ISL6557A is capable of executing on-the-fly output-
voltage changes. At the beginning of the phase-1 switching
cycle (defined in the section entitled
PWM Operation
), the
ISL6557A checks for a change in the VID code. The VID
code is the bit pattern present at pins VID4-VID0 as outlined
in
Voltage Regulation
. If the new code remains stable for
another full cycle, the ISL6557A begins incrementing the
reference by making 25mV change every two switching
cycles until the it reaches the new VID code.
Since the ISL6557A recognizes VID-code changes only at
the beginnings of switching cycles, up to one full cycle may
pass before a VID change registers. This is followed by a
one-cycle wait before the output voltage begins to change.
Thus, the total time required for a VID change, t
DV
, is
FIGURE 9. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
-
+
I
AVG
REFERENCE
VOLTAGE
EXTERNAL CIRCUIT
ISL6557A INTERNAL CIRCUIT
COMP
C
C
R
C
R
FB
FB
IOUT
VDIFF
ERROR AMPLIFIER
V
COMP
V
RAMP
I
RAMP
IDEAL DIODES
t
DELAY
T
R
FB
160
1
10
6
×
----------------------------------------
+
--------------------------------------------------
580
μ
s
=
=
(EQ. 6)
t
RAMP1
T
----------
t
DELAY
=
5.27ms
=
(EQ. 7)
t
RAMP2
T
SS
t
RAMP1
t
DELAY
=
2.34ms
=
(EQ. 8)
FIGURE 10. SOFT-START WAVEFORMS FOR ISL6557A
BASED MULTI-PHASE BUCK CONVERTER
1ms/DIV
EN, 5V/DIV
VOUT, 500mV/DIV
t
DELAY
t
RAMP1
t
RAMP2
FIGURE 11. DYNAMIC-VID WAVEFORMS FOR 500KHZ
ISL6557A BASED MULTI-PHASE BUCK
CONVERTER
5
μ
s/DIV
V
REF
, 100mV/DIV
V
OUT
, 100mV/DIV
1.3V
V
ID
, 5V/DIV
01110
00010
1.3V
VID CHANGE OCCURS
ANYWHERE HERE
ISL6557A
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