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參數(shù)資料
| 型號： | ISL6563IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Two-Phase Multi-Phase Buck PWM Controller with Integrated MOSFET Drivers |
| 中文描述： | SWITCHING CONTROLLER, 255 kHz SWITCHING FREQ-MAX, PQCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220-VGGD-2, QFN-24 |
| 文件頁數(shù)： | 15/19頁 |
| 文件大?。?/td> | 516K |
| 代理商： | ISL6563IRZ |
15
FN9126.6
April 13, 2005
The feedback resistor, R
1
, has already been chosen as
outlined in
Load Line Regulation
. Select a target bandwidth
for the compensated system, f
0
. The target bandwidth must
be large enough to ensure adequate transient performance,
but smaller than 1/3 of the per-channel switching frequency
(75kHz in this case). The values of the compensation
components depend on the relationships of f
0
to the output
filter, LC, double pole frequency and the ESR zero frequency
of the bulk output capacitor bank. For each of the three
cases defined below, there is a separate set of equations for
the compensation components.
In the previous equations, L is the per-channel filter
inductance divided by the number of active channels, C is
the total bulk output capacitance, ESR is the equivalent
series resistance of the bulk output filter capacitance, and
V
PP
is the peak-to-peak sawtooth signal amplitude (see
Electrical Specifications)
.
Once selected, the compensation values assure a stable
converter with reasonable transient performance. C
1
is
needed to cut down the high frequency error amplifier gain
and reduce the noise the PWM comparator sees. Keep a
position available for C
1
, and install a 10pF to 47pF in case
jitter is noted.
Output Filter Design
The output inductors and the output capacitor bank together
to form a low-pass filter responsible for smoothing the
square wave voltage at the phase nodes. Additionally, the
output capacitors must also provide the energy required by a
fast transient load during the short interval of time required
by the controller and power train to respond. Because it has
a low bandwidth compared to the switching frequency, the
output filter limits the system transient response leaving the
output capacitor bank to supply the load current or sink the
inductor currents, all while the current in the output inductors
increases or decreases to meet the load demand.
In high-speed converters, the output capacitor bank is
amongst the costlier (and often the physically largest) parts
of the circuit. Output filter design begins with consideration
of the critical load parameters: maximum size of the load
step,
I, the load-current slew rate, di/dt, and the maximum
allowable output voltage deviation under transient loading,
V
MAX
. Capacitors are characterized according to their
capacitance, ESR, and ESL (equivalent series inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-
voltage deviation is less than the allowable maximum.
Neglecting the contribution of inductor current and regulator
response, the output voltage initially deviates according to
the following equation:
The filter capacitor must have sufficiently low ESL and ESR
so that
V <
V
MAX
.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
FIGURE 8. COMPENSATION CONFIGURATION FOR ISL6563
CIRCUIT
I
COMP
C
2
R
2
R
1
FB
V
OUT
-
+
V
DROOP
C
1
Case 1:
2
π
LC
-----------------------
f
0
>
R
2
R
1
2
π
f
V
0.66 V
IN
------------------------------------------------
=
C
2
0.66 V
2
V
PP
R
FB
f
0
------------------------------------------------
=
Case 2:
2
π
LC
-----------------------
f
0
2
C ESR
---------------------------------
≤
≤
R
2
R
1
V
----------------------------------------------------
2
π
(
)
2
f
2
LC
IN
=
C
2
0.66 V
V
PP
R
1
2
π
(
)
f
0
LC
--------------------------------------------------------------------
=
Case 3:
C
2
0.66 V
ESR
2
π
V
PP
R
1
f
0
C
L
--------------------------------------------------------
=
f
0
2
π
C ESR
---------------------------------
>
R
2
R
1
2
π
f
V
L
IN
-------------------------------------------
=
V
ESL
(
)
di
dt
----
ESR
(
)
I
+
≈
ISL6563
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| ISL6563IRZ-T | 功能描述:電流型 PWM 控制器 P6 TWO PHS CONT INTEGRTD DRVRS DESKT RoHS:否 制造商:Texas Instruments 開關(guān)頻率:27 KHz 上升時間: 下降時間: 工作電源電壓:6 V to 15 V 工作電源電流:1.5 mA 輸出端數(shù)量:1 最大工作溫度:+ 105 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSSOP-14 |
| ISL6564ACRZ | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6564ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6564AIRZ | 功能描述:IC REG CTRLR BUCK PWM VM 40-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
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