參數(shù)資料
型號: ISL6565ACBZ
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application
中文描述: SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO28
封裝: ROHS COMPLIANT, PLASTIC, MS-013-AE, SOIC-28
文件頁數(shù): 11/28頁
文件大小: 722K
代理商: ISL6565ACBZ
11
Figures 19 and 20 in the section entitled
Input Capacitor
Selection
can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
optimal input capacitor solution.
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6565A, ISL6565B is three. One switching cycle is defined
as the time between PWM1 pulse termination signals. The
pulse termination signal is the internally generated clock
signal that triggers the falling edge of PWM1. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
PWM1 to go low. The PWM1 transition signals the channel-1
MOSFET driver to turn off the channel-1 upper MOSFET
and turn on the channel-1 synchronous MOSFET. In the
default channel configuration, the PWM2 pulse terminates
1/3 of a cycle after the PWM1 pulse. The PWM3 pulse
terminates 1/3 of a cycle after PWM2.
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle after
the PWM1 pulse terminates.
Once a PWM pulse transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V
COMP
, minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 6. When the modified
V
COMP
voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sampling
During the forced off-time, following a PWM transition low,
the current-sense amplifier uses the ISEN inputs to
reproduce a signal proportional to the inductor current, I
L
.
No matter which current-sense method is employed, the
sense current (I
SEN
) is simply a scaled version of the
inductor current. The sample window opens exactly 1/6 of
the switching period, t
SW
, after the PWM transitions low. The
sample window then stays open for a fixed amount of time,
t
SAMPLE
, and is equal to 1/6 of the switching period, t
SW
as
illustrated in Figure 3.
The sampled current, at the end of the t
SAMPLE
, is
proportional to the inductor current and is held until the next
switching period sample. The sampled current is used for
current balance, load-line regulation, and overcurrent
protection.
Current Sensing
The ISL6565A supports MOSFET r
DS(ON)
current sensing,
while the ISL6565B supports inductor DCR current sensing.
The internal circuitry, shown in Figures 4 and 5, represent
channel n of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 pin, as
described in the
PWM Operation
section.
MOSFET r
DS(ON)
SENSING (ISL6565A ONLY)
The ISL6565A senses the channel load current by sampling
the voltage across the lower MOSFET r
DS(ON)
, as shown in
Figure 4. A ground-referenced operational amplifier, internal
to the ISL6565A, is connected to the PHASE node through a
resistor, R
ISEN
. The voltage across R
ISEN
is equivalent to
the voltage drop across the r
DS(ON)
of the lower MOSFET
while it is conducting. The resulting current into the ISEN pin
is proportional to the channel current, I
L
. The ISEN current is
sampled and held as described in the
Current Sampling
section. From Figure 4, the following equation for I
n
is
derived where I
L
is the channel current.
t
SAMPLE
t
----------
SW
------------------
=
=
(EQ. 3)
FIGURE 3. SAMPLE AND HOLD TIMING
TIME
PWM
I
L
I
SEN
NEW SAMPLE CURRENT
t
SAMPLE
SWITCHING PERIOD
OLD SAMPLE
CURRENT
I
n
I
L
r
ISEN
)
-R
=
(EQ. 4)
ISL6565A, ISL6565B
相關(guān)PDF資料
PDF描述
ISL6565ACRZ Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application
ISL6565ACV Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application
ISL6565ACVZ Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application
ISL6565B Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application
ISL6565BCB Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application
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參數(shù)描述
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ISL6565ACR-T 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:100% 電源電壓:8.2 V ~ 30 V 降壓:無 升壓:無 回掃:是 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:0°C ~ 70°C 封裝/外殼:8-DIP(0.300",7.62mm) 包裝:管件 產(chǎn)品目錄頁面:1316 (CN2011-ZH PDF)
ISL6565ACRZ 功能描述:IC REG CTRLR BUCK PWM VM 28-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC(0.154",3.90mm 寬) 包裝:帶卷 (TR)
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