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參數(shù)資料
| 型號(hào)： | ISL6565BCB |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Multi-Phase PWM Controller with Precision rDS(ON) or DCR Current Sensing for VR10.X Application |
| 中文描述： | SWITCHING CONTROLLER, 1500 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | PLASTIC, MS-013-AE, SOIC-28 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大小： | 722K |
| 代理商： | ISL6565BCB |
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15
As shown in Figure 7, a current proportional to the average
current in all active channels, I
AVG
, flows from FB through a
load-line regulation resistor, R
FB
. The resulting voltage drop
across R
FB
is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
In most cases, each channel uses the same component
values to sense current. If this is the case you can derive a
more complete equation for V
DROOP
for each current sense
method being used.
Output-Voltage Offset Programming
The ISL6565A, ISL6565B allows the designer to accurately
adjust the offset voltage by connecting a resistor, R
OFS
,
from the OFS pin to VCC or GND. When R
OFS
is connected
between OFS and VCC, the voltage across it is regulated to
2.0V. This causes a proportional current (I
OFS
) to flow into
the OFS pin and out of the FB pin. If R
OFS
is connected to
ground, the voltage across it is regulated to 0.5V, and I
OFS
flows into the FB pin and out of the OFS pin. The offset
current flowing through the resistor between VDIFF and FB
will generate the desired offset voltage which is equal to the
product (I
OFS
x R
FB
). These functions are shown in Figures
8 and 9.
Once the desired output offset voltage has been determined,
use the following formulas to set R
OFS
:
For Positive Offset (connect R
OFS
to GND):
For Negative Offset (connect R
OFS
to VCC):
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs. The core-voltage regulator is required to monitor the
DAC inputs and respond to on-the-fly VID changes in a
controlled manner supervising a safe output voltage transition
without discontinuity or disruption.
V
DROOP
I
AVG
R
FB
=
(EQ. 10)
V
DROOP
I
---N
r
ISEN
)
-R
FB
=
(EQ. 11)
(ISL6565A ONLY)
r
DS(ON)
SENSING
V
DROOP
I
N
-------------
K
R
ISEN
-----------------
R
FB
=
(EQ. 12)
(ISL6565B ONLY)
DCR SENSING
(EQ. 13)
R
OFS
0.5
V
OFFSET
--------------------------
=
(EQ. 14)
R
OFS
2
R
×
V
OFFSET
--------------------------
=
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
2.0V
GND
R
OFS
R
FB
VDIFF
ISL6565A, ISL6565B
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
V
OFS
-
+
I
OFS
E/A
FB
OFS
VCC
GND
+
-
+
-
0.5V
2.0V
VCC
R
OFS
R
FB
VDIFF
ISL6565A, ISL6565B
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VREF
V
OFS
+
-
I
OFS
ISL6565A, ISL6565B
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