參數(shù)資料
型號(hào)： ISL6590
廠商： Intersil Corporation
英文描述： Dual Low-Noise Wide-Bandwidth Precision Amplifier 8-PDIP -40 to 85
中文描述： 數(shù)字多相位PWM控制器為核心電壓調(diào)節(jié)
文件頁(yè)數(shù)： 14/24頁(yè)
文件大?。?/td> 1525K
代理商： ISL6590
14
ISL6580 Calibration
Prior to calibration, the status of each ISL6580 is checked.
The input supply voltage is checked by polling the status of
the under-voltage lockout in the status registers of the
ISL6580s. Other faults are also checked. If a fault is
detected during or after calibration, the system state may be
frozen while fault processing takes over to resolve the error.
To calibrate the voltage ADC, the VID is set to the same
voltage as the external VID setting. Voltage ADC calibration
is initiated by setting the device that is hard wired for
Regulation mode into calibration mode. This should be
device #1. During calibration, any offset voltage internal to
the ADC is output on the ERR serial line. The error is stored
in the non-volatile memory. Then the ISL6590 changes
themode of the ISL6580 to normal operation and calibration
is complete.
ISL6580 Softstart
The system is slowly brought out of the no output voltage
open loop state by sending a small PWM pulse width to the
ISl6580s. A fixed time period and step size is used to bring
the output voltage into the lower range of the voltage ADC.
Once the voltage ADC begins reading voltage, a fixed V
step
step size is used (25mV). After each V
step
step is
performed, the output voltage must settle within a +/-
(V
step
/2) mV window of the specified VID voltage before
stepping to the next output voltage setting. The stepping
continues until the final voltage is reached.
Power On Reset
The ISL6590 controller performs a Power On Reset function
internally. It holds all internal logic in a reset state until the
Vdd (3.3V) exceeds a threshold. While in the reset state all
PWM and NDRIVE signals are held at ground and all
MOSFETs are OFF.
Duty Cycle Limit
The ISL6590 limits the on time of the upper FETs. The
system designer can set the maximum ON time with
PowerCode software The value is put in as a percentage. If
the duty cycle reaches this percentage, the top side FET
turns off until the next cycle.
FIGURE 11. ENUMERATION TIMING DIAGRAM
MHz Power IC Configuration Process
First the master will initiate “config call” by sending a “10’h00” address
All of the slaves should “ACK” because every MHz Power IC register contains 0” after reset
The ID is then sent out during the data cycle.
The process is repeated until all (N) of the devices are configured.
10 clocks
8 Clocks
SCLK
Repeat for N-1 devices
SDATA
ID for Power IC 1
("ID" register enable)
MHz Power IC 1 ID register enable
Ack
Stop
"0000000000"
Ack
n
Start
Address Cycle
Data Cycle
PWM1
Configcall
R/W
Directio
TABLE 10. SERIAL BUS ID MAPPING
BSB ID
DESCRIPTION
00h
“config call”
01h
Power IC 1
02h
Power IC 2
03h
Power IC 3
04h
Power IC 4
05h
Power IC 5
06h
Power IC 6
09-1Fh
Reserved
ISL6590
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