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參數(shù)資料
| 型號： | ISL6596IRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 功率晶體管 |
| 英文描述： | Synchronous Rectified MOSFET Driver |
| 中文描述： | HALF BRDG BASED MOSFET DRIVER, PDSO10 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220, DFN-10 |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 301K |
| 代理商： | ISL6596IRZ-T |
5
FN9240.0
November 2, 2005
Functional Pin Description
Note: Pin numbers refer to the SOIC package. Check
diagram for corresponding DFN pinout.
UGATE (Pin 1)
Upper gate drive output. Connect to gate of high-side
N-Channel power MOSFET. A gate resistor is never
recommended on this pin, as it interferes with the operation
shoot-through protection circuitry.
BOOT (Pin 2)
Floating bootstrap supply pin for the upper gate drive.
Connect a bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge
used to turn on the upper MOSFET. See the
Bootstrap
Considerations
section for guidance in choosing the
appropriate capacitor value.
PWM (Pin 3)
The PWM signal is the control input for the driver. The PWM
signal can enter three distinct states during operation, see the
Tri-state PWM Input
section for further details. Connect this pin
to the PWM output of the controller.
GND (Pin 4)
Ground pin. All signals are referenced to this node.
LGATE (Pin 5)
Lower gate drive output. Connect to gate of the low side
N-Channel power MOSFET. A gate resistor is never
recommended on this pin, as it interferes with the operation
shoot-through protection circuitry.
VCC (Pin 6)
Connect this pin to a +5V bias supply. Locally bypass with a
high quality ceramic capacitor to ground.
VCTRL (Pin 7)
This pin sets the PWM logic threshold. Connect this pin to
3.3V source for 3.3V PWM input
and pull it to 5V source for
5V PWM input.
PHASE (Pin 8)
Connect this pin to the source of the upper MOSFET. This
pin provides the return path for the upper gate driver current.
Thermal Pad (in DFN only)
The metal pad underneath the center of the IC is a thermal
substrate. The PCB “thermal land” design for this exposed
die pad should include vias that drop down and connect to
one or more buried copper plane(s). This combination of
vias for vertical heat escape and buried planes for heat
spreading allows the DFN to achieve its full thermal
potential. This pad should be either grounded or floating,
and it should not be connected to other nodes. Refer to
TB389 for design guidelines.
Timing Diagram
PWM
UGATE
LGATE
t
PDLL
t
PDHU
t
RU
t
PDLU
t
PDHL
t
RL
1V
t
RU
t
FU
t
FL
1V
t
PTS
t
TSSHD
t
TSSHD
t
PTS
FIGURE 1. TIMING DIAGRAM
50% of VCC
ISL6596
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