參數資料
| 型號： | ISL76322ARZ |
| 廠商： | Intersil |
| 文件頁數： | 2/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO SERDES LONG 16BIT 48QFN |
| 標準包裝： | 260 |
| 功能： | 串行器/解串器 |
| 輸入類型： | RGB |
| 輸出類型： | 串行 |
| 輸入數： | 16 |
| 輸出數： | 1 |
| 電源電壓： | 1.8V, 3.3V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 管件 |
ISL76322
10
December 21, 2013
FN7611.2
Applications
Detailed Description and Operation
A pair of ISL76322 SERDES transports 16-bit parallel video for
the ISL76322 along with auxiliary data over a single 100
Ω
differential cable either to a display or from a camera. Auxiliary
data is transferred in both directions every video frame. This
feature can be used for remote configuration and telemetry.
The benefits include lower EMI, lower costs, greater reliability and
space savings. The same device can be configured to be either a
serializer or deserializer by setting one pin (VIDEO_TX), simplifying
inventory. RGBA/C, VSYNC, HSYNC, and DATAEN pins are inputs in
serializer mode and outputs in deserializer mode.
The video data presented to the serializer on the parallel LVCMOS
bus is serialized into a high-speed differential signal. This
differential signal is converted back to parallel video at the
remote end by the deserializer. The Side Channel data (auxiliary
data) is transferred between the SERDES pair during the first two
lines of the vertical video blanking interval.
When the side-channel is enabled, which is the default, there will
be a number of PCLK cycles uncertainty from frame-to-frame.
This should not cause sync problems with most displays as this
occurs during the vertical front porch of the blanking period.
When properly configured, the SERDES link supports end-to-end
transport with fewer than one error in 1010 bits.
Differential Signals and Termination
The ISL76322 serializes the 16-bit parallel data plus 3 sync
signals at 20x the PCLK_IN frequency. The extra 2 bits per word
come from the 8b/10b encoding scheme which helps create the
highest quality serial link.
The high bit rate of the differential serial data requires special
care in the layout of traces on PCBs, in the choice and assembly
of connectors, and in the cables themselves.
PCB traces need to be adjacent, matched in length and drawn to
result in a differential 100 controlled impedance. For best EMI
performance, the cable should be low loss and have a differential
100 impedance. The maximum cable length for a functioning
link is dependent on the PCLK_IN frequency, the cable loss and
impedance, as well as the pre-emphasis and equalization
settings. Functioning links of 25 meters are often possible at the
maximum frequency.
SERIOP and SERION pins incorporate internal differential
termination of the serial signal lines.
SERIO Pin AC-Coupling
AC-coupling minimizes the effects of DC common mode voltage
difference and local power supply variations between two
SERDES. The serializer outputs DC balanced 8b/10b line code,
which allows AC-coupling.
The AC-coupling capacitor on SERIO pins must be 27nF on the
serializer board and 27nF on the deserializer board. The value of the
AC-coupling capacitor is very critical since a value too small will
attenuate the high-speed signal at low clock rate. A value too big will
slow down the turn around time for the side-channel. It is an
advantage to have the pair of capacitors as closely matched as
possible.
Receiver Reference Clock (REF_CLK)
The reference clock (REF_CLK) for the PLL is fed into PCLK_IN
pin. REF_CLK is used to recover the clock from the high-speed
serial stream. REF_CLK is very sensitive to any instability. The
following conditions must be met at all times after power is
applied to the deserializer, or else the deserializer may need a
manual reset:
VDD must be applied and stable
REF_CLK frequency must be within the limits specified
REF_CLK amplitude must be stable
A simple 3.3V CMOS crystal oscillator can be used for REF_CLK
Power Supply Sequencing
The 3.3V supply must be higher than the 1.8V supply at all times,
including during power-up and power-down. To meet this
requirement, the 3.3V supply must be powered up before the
1.8V supply.
For the deserializer, REF_CLK must not be applied before the
device is fully powered up. Applying REF_CLK before power-up
may require the deserializer to be manually reset. A 10ms delay
after the 1.8V supply is powered up guarantees normal
operation.
Power Supply Bypassing and Layout
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or locked to
an incoming signal. It is important that the various supplies
(VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a
wide range of frequencies, from below the typical loop bandwidth
of the PLL to approaching the signal bit rate of the serial data. A
combination of different values of capacitors from 1000pF to
5F or more with low ESR characteristics is generally required.
The parallel LVCMOS VDD_IO supply is inherently less sensitive,
but since the RGB and SYNC/DATAEN signals can all swing on the
same clock edge, the current in these pins, and the
corresponding GND pins, can undergo substantial current flow
changes. Once again, a combination of different values of
capacitors over a wide range, with low ESR characteristics, is
desirable.
A set of arrangements of this type is shown in Figure 5, where
each supply is bypassed with a ferrite-bead-based choke, and a
range of capacitors. A “choke” is preferable to an “inductor” in
this application, since a high-Q inductor will be likely to cause one
or more resonances with the shunt capacitors, potentially
causing problems at or near those frequencies, while a “l(fā)ossy”
choke will reflect a high impedance over a wide frequency range.
The higher value capacitor, in particular, needs to be chosen
carefully, with special care regarding its ESR. Very good results
can be obtained with multilayer ceramic capacitors (available
from many suppliers) and generally in small outlines (such as the
1210 outline suggested in the schematic shown in Figure 5),
which provide good bypass capabilities down to a few m
Ω at
1MHz to 2MHz. Other capacitor technologies may also be
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