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參數(shù)資料
| 型號： | ISL8540 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | DC/DC Power Switching Regulator |
| 中文描述： | DC/DC電源開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 952K |
| 代理商： | ISL8540 |
13
FN6495.4
September 18, 2007
Practically, it can be approximated if an impedance vs
frequency curve is given for a specific capacitor (C):
The ESL of the capacitors becomes a concern when
designing circuits that supply power to loads with high rates
of change in the current.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by Equation 7:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient. Use
Δ
I of
approximately 30% of I
OUT
is a good compromise.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL8540 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. Equation 8 gives
the approximate response time interval for application and
removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Rectifier Selection
Current circulates from ground to the junction of the
MOSFET and the inductor when the high-side switch is off.
As a consequence, the polarity of the switching node is
negative with respect to ground. This voltage is
approximately -0.5V (a Schottky diode drop) during the off
time. The rectifier's rated reverse breakdown voltage must
be at least equal to the maximum input voltage, preferably
with a 20% derating factor. The power dissipation is:
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the VIN’s pin. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the upper MOSFET
turns on. Place the small ceramic capacitors physically close
to the VIN and PGND pins.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current through the input capacitors
may be closely approximated through Equation 10:
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
Feedback Compensation
Figure 28 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The error
amplifier output (V
E/A
) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V
IN
at the LX node. The PWM
wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at f
LC
and a zero at f
ESR
. The DC Gain of
ESL
C 2
π
f
res
)
2
-----------------1
=
where f
res
is the frequency where the lowest impedance
is achieved (resonant frequency).
(EQ. 6)
Δ
I
=
V
IN
- V
OUT
Fs x L
V
OUT
V
IN
Δ
V
OUT
=
Δ
I
x
ESR
x
(EQ. 7)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 8)
P
D
W
[
]
I
OUT
V
D
1
V
IN
---------------
–
=
where V
D
is the voltage of the Schottky diode = 0.5V to 0.7V
(EQ. 9)
V
IN
-------------
I
OUTMAX
2
1
V
IN
-------------
–
×
------
V
V
OSC
–
----------------------------
V
IN
-------------
×
2
×
+
×
(EQ. 10)
ISL8540
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