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參數(shù)資料
| 型號(hào)： | ISL870XAEVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Adjustable Quad Sequencer |
| 中文描述： | 可調(diào)四序 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 285K |
| 代理商： | ISL870XAEVAL1 |
3
FN6381.0
October 12, 2006
Pin Descriptions
PINS
PIN NAME
FUNCTION DESCRIPTION
8700A 8701A 8702A 8703A 8704A 8705A
NA
1
NA
1
NA
1
ENABLE#_D Active low open drain sequenced output. Sequenced on after ENABLE#_C and first output
to sequence off for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
ENABLE_D Active high open drain sequenced output. Sequenced on after ENABLE_C and first output
to sequence off for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
ENABLE#_C Active low open drain sequenced output. Sequenced on after ENABLE#_B and sequenced
off after ENABLE#_D for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
ENABLE_C Active high open drain sequenced output. Sequenced on after ENABLE_B and sequenced
off after ENABLE_D for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
ENABLE#_B Active low open drain sequenced output. Sequenced on after ENABLE#_A and sequenced
off after ENABLE#_C for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
ENABLE_B Active high open drain sequenced output. Sequenced on after ENABLE_A and sequenced
off after ENABLE_C for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
ENABLE#_A Active low open drain sequenced output. Sequenced on after CTIME period and sequenced
off after ENABLE#_B for the ISL8701A, ISL8703A, ISL8705A. Tracks V
IN
upon bias.
ENABLE_A Active high open drain sequenced output. Sequenced on after CTIME period and
sequenced off after ENABLE_B for the ISL8700A, ISL8702A, ISL8704A. Pulls low with V
IN
< 1V.
1
NA
1
NA
1
NA
NA
2
NA
2
NA
2
2
NA
2
NA
2
NA
NA
3
NA
3
NA
3
3
NA
3
NA
3
NA
NA
4
NA
4
NA
4
4
NA
4
NA
4
NA
5
5
5
5
5
5
OV
The voltage on this pin must be under its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
6
6
6
6
6
6
UV
The voltage on this pin must be over its 1.22V Vth or the four ENABLE outputs will be
immediately pulled down. Conversely the 4 ENABLE# outputs will be released to be pulled
high via external pull-ups.
7
7
7
7
7
7
GND
IC ground.
NA
NA
8
8
8
8
FAULT
The V
IN
voltage when not within the desired UV to OV window will cause FAULT to be
released to be pulled high to a voltage equal to or less than V
IN
via an external resistor.
This pin provides a sequence on signal input with a high input. Internally pulled high to ~2.4V.
NA
NA
9
9
NA
NA
SEQ_EN
NA
NA
NA
NA
9
9
SEQ_EN#
This pin provides a sequence on signal input with a low input. Internally pulled high to ~2.4V.
10
10
10
10
10
10
TIME
This pin provides a 2.6μA current output so that an adjustable V
IN
valid to sequencing on
and off start delay period is created with a capacitor to ground.
11
11
11
11
11
11
TB
A resistor connected from this pin to ground determines the time delay from ENABLE_A
being active to ENABLE _B being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
12
12
12
12
12
12
TC
A resistor connected from this pin to ground determines the time delay from ENABLE_B
being active to ENABLE _C being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
13
13
13
13
13
13
TD
A resistor connected from this pin to ground determines the time delay from ENABLE_C
being active to ENABLE _D being active on turn-on and also going inactive on turn-off via
the SEQ_IN input.
14
14
14
14
14
14
V
IN
IC Bias Pin Nominally 3.3V to 24V
This pin requires a 1
μ
F decoupling capacitor close to IC pin.
ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A
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