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參數(shù)資料
| 型號： | ISL8723 |
| 廠商： | Intersil Corporation |
| 英文描述： | Power Sequencing Controllers |
| 中文描述： | 電源順序控制器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 276K |
| 代理商： | ISL8723 |
5
FN6413.0
December 21, 2006
ISL8723, ISL8724 Descriptions and
Operation
The ISL8723 and ISL8724 sequencers are quad voltage
sequencing controllers designed for use in multiple-voltage
systems requiring power sequencing of various supply
voltages. Individual voltage rails are gated on and off by
external N-Channel MOSFETs, the gates of which are
driven by an internal charge pump to ~V
DD
+5.6V (VQP) in
a user programmed sequence.
With the ISL8723 the ENABLE must be asserted high and
all four voltages to be sequenced must be above their
respective user programmed Under Voltage Lock Out
(UVLO) levels before programmed output turn on
sequencing can begin. Sequencing and delay
determination is accomplished by the choice of external
cap values on the DLY_ON and DLY_OFF pins. The
SYSRST# goes high once all 4 UVLO inputs and ENABLE
are satisfied. Once all 4 UVLO inputs and ENABLE are
satisfied for 10ms, the four DLY_ON caps are
simultaneously charged with 1
μ
A current sources to the
DLY_Vth level of 1.28V. As each DLY_ON pin reaches the
DLY_Vth level its associated GATE will then turn-on with a
10
μ
A source current to the VQP voltage of VDD+5.6V.
Thus all four GATEs will sequentially turn on. Once at
DLY_Vth the DLY_ON pins will discharge to be ready when
next needed. After the entire turn on sequence has been
completed and all GATEs have reached the charge
pumped voltage (VQP), a 160ms delay is started to ensure
stability after which the RESET# output will be released to
go high. Subsequent to turn-on, if any input falls below its
UVLO point for longer than the glitch filter period, T
FIL
(~7
μ
s) this is considered a fault. RESET#, SYSRST# and
all GATEs are simultaneously pulled low. In this mode the
GATEs are pulled low with ~75mA. Normal shutdown mode
is entered when no UVLO is violated and the ENABLE is
deasserted. When ENABLE is deasserted, RESET# is
asserted and pulled low. Next, all four shutdown ramp caps
on the DLY_OFF pins are charged with a 1
μ
A source and
when any ramp-cap reaches DLY_Vth, a latch is set and a
10
μ
A current is sunk on the respective GATE pin to turn off
its external MOSFET. When the falling GATE voltage is
approximately 1.5V, the GATE is pulled down the rest of the
way at a higher current level to ensure a hard turn-off. Each
individual external FET is thus turned off removing the
voltages from the load in the programmed sequence. The
SYSRST# will pull low concurrent with the last GATE being
pulled low.
The ISL8723 and ISL8724 have the same functionality
except for the complimentary ENABLE active polarity with
the ISL8724 having an ENABLE# input. Additionally the
ISL8723 also has a low power sleep state when disabled.
Upon bias the SYSRST# and RESET# pins are held low
before bias voltage = 1V.
The SYSRST# has both an input and output function. As an
output the SYSRST# pin is useful when implementing
multiple sequencers in a design needing simultaneous
shutdown as with a kill switch across all sequencers. Once
any UVLO is unsatisfied for longer than T
FIL
the related
SYSRST# will pull low and pull all other SYSRST# pins low
that are on a common connection thus unconditionally
shutting down all outputs across multiple sequencers. As
an input, if it is pulled low all GATEs will be unconditionally
shut off and RESET# pulled low, see Figure 17. This pin
can also be used as a ‘no wait’ enabling input, if all inputs
(ENABLE and UVLO) are satisfied it does not wait through
SYSRST# Output Capacitance
Cout_srst
-
10
-
pF
SYSRST# Low to GATE Turn-off
T
delSYS_G_1
GATE = 80% of V
DD
+5V
-
40
-
ns
SYSRST# High to GATE Turn-on
T
delSYS_G_2
GATE = 50% of V
DD
+5V
-
0.4
-
ms
GATE
GATE Turn-On Current
I
GATEon
GATE = 0V
8.3
10.2
12.5
μ
A
GATE Turn-Off Current
I
GATEoff_l
GATE = V
DD
, Disabled
-12.5
-10.2
-8.3
μ
A
GATE Current Range
I
GATE_range
Within IC I
GATE
max-min
-
0.6
3
μ
A
GATE Pull-Down High Current
I
GATEoff_h
GATE = V
DD
, UVLO = 0V
-
75
-
mA
GATE High Voltage
V
GATEh5
V
DD
= 5V
V
DD
+5.3V
V
DD
+5.6V
-
V
GATE Low Voltage
V
GATEl
Gate Low Voltage, V
DD
= 1V
-
0.01
0.1
V
BIAS
IC Supply Current
I
VDD_5V
V
DD
= 5V, Enabled and static
-
0.27
0.31
mA
ISL8723 Stand By IC Supply Current
I
VDD_sb
V
DD
= 5V, ENABLE = 0V
-
30
40
μ
A
V
DD
Power On Reset
V
DD
_POR
V
DD
rising
-
2.2
2.41
V
Electrical Specifications
V
DD
= 3.3V to +5V, T
A
= T
J
= -40°C to +85°C, Unless Otherwise Specified.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ISL8723, ISL8724
相關PDF資料 |
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|---|---|
| ISL8723EVAL1 | Power Sequencing Controllers |
| ISL8723IRZ | Power Sequencing Controllers |
| ISL8723IRZ-T | Power Sequencing Controllers |
| ISL8724 | Power Sequencing Controllers |
| ISL8724IRZ | Power Sequencing Controllers |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL8723EVAL1 | 功能描述:EVAL BOARD 1 FOR ISL8723 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| ISL8723IRZ | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL8723IRZR5369 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL8723IRZ-T | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL8723IRZ-TR5369 | 制造商:Intersil Corporation 功能描述: |
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