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參數(shù)資料
| 型號(hào)： | ISL8724 |
| 廠商： | Intersil Corporation |
| 英文描述： | Power Sequencing Controllers |
| 中文描述： | 電源順序控制器 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 276K |
| 代理商： | ISL8724 |
2
FN6413.0
December 21, 2006
FIGURE 1. TYPICAL ISL8723 APPLICATION USAGE
AOUT
AIN
BIN
CIN
DIN
BOUT
COUT
DOUT
UVLO_B
UVLO_C
UVLO_A
UVLO_D
A
D
D
D
D
D
D
D
D
ENABLE
SYSRST#
GROUND
B
C
D
RESET#
VDD
G
G
G
G
Pin Descriptions
PIN
#
PIN NAME
FUNCTION
DESCRIPTION
23
VDD
Chip Bias
Bias IC from nominal 2.5V to 5V
10
GND
Bias Return
IC ground
1
ENABLE/
ENABLE#
Input to start on/off
sequencing.
Input to initiate the start of the programmed sequencing of supplies on or off. Enable functionality is
disabled for 10ms after UVLO is satisfied. ISL8723 has ENABLE. ISL8724 has ENABLE#.
24
RESET#
RESET# Output
RESET# provides a high signal ~160ms after all GATEs are fully enhanced. This delay is for stabilization
of output voltages. RESET# will assert low upon any UVLO not being satisfied or ENABLE/ENABLE#
being deasserted. The RESET# output is an open drain N-channel FET and is guaranteed to be in the
correct state for VDD down to 1V and is filtered to ignore fast transients on VDD and UVLO_X.
20
UVLO_A
Under Voltage Lock
Out/Monitoring
Input
These inputs provide for a programmable UV lockout referenced to an internal 0.631V reference and
are filtered to ignore short (<7μs) transients below programmed UVLO level.
12
UVLO_B
17
UVLO_C
14
UVLO_D
21
DLY_ON_A
Gate On Delay
Timer Output
Allows for programming the delay and sequence for V
OUT
turn-on using a capacitor to ground. Each
cap is charged with 1μA, 10ms after turn-on initiated by ENABLE/ENABLE# with an internal current
source providing delayed enhancement of the associated FETs GATE to turn-on.
8
DLY_ON_B
16
DLY_ON_C
15
DLY_ON_D
18
DLY_OFF_A
Gate Off Delay
Timer Output
Allows for programming the delay and sequence for V
OUT
turn-off through ENABLE/ENABLE# via a
capacitor to ground. Each cap is charged with a 1μA internal current source to an internal reference
voltage causing the corresponding gate to be pulled down thus turning-off the FET.
13
DLY_OFF_B
3
DLY_OFF_C
4
DLY_OFF_D
2
GATE_A
FET Gate Drive
Output
Drives the external FETs with a 10μA current source to soft start ramp into the load. During sequence
off, 10μA is sunk from this pin to control the FET turn-off. During a turn-off due to a fault, the gate will
sink ~75mA to ensure a rapid turn-off.
5
GATE_B
6
GATE_C
7
GATE_D
ISL8723, ISL8724
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