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參數資料
| 型號： | ISL88013IH531Z-TK |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 5 Ld Voltage Supervisors with Adjustable Power-On Reset, Dual Voltage Monitoring or Watchdog Timer Capability |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO5 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MO-178AA, SOT-23, SC-74, 5 PIN |
| 文件頁數： | 6/12頁 |
| 文件大?。?/td> | 223K |
| 代理商： | ISL88013IH531Z-TK |
6
FN8093.1
December 14, 2006
Pin Description
RST
The push-pull RST output is set to V
DD
(HIGH) whenever 1)
the device is first powered up, 2) either V
DD
or the voltage on
VMON falls below their respective minimum voltage sense
levels, 3) MR is asserted or 4) the watchdog timeout expires.
RST/MR
This pin functions as both a reset output and a manual reset
input. The RST output functions identically to the
complementary RST output but is an open drain output that
is pulled to GND (LOW) when reset is asserted. The MR
input is an active-low debounced input to which a user can
connect a push-button to add manual reset capability or
drive with active low signal from a controller.
V
DD
The V
DD
pin is the power supply terminal. It is monitored by
the ISL88011, ISL88012 and ISL88013. For these devices,
the voltage at this pin is compared against an internal
factory-programmed voltage trip point, V
THVDD
. A reset is
first asserted when the device is initially powered up to
ensure that the power supply has stabilized. Thereafter,
reset is again asserted whenever V
DD
falls below V
THVDD
.
The device is designed with hysteresis to help prevent
chattering due to noise.
VMON
The VMON pin on the ISL88012, ISL88014 and ISL88015 is
a monitored input voltage that is user-adjustable. The
voltage at this pin is compared against an internal 600mV
reference voltage (V
THVMON
) and a reset is asserted
whenever the monitored voltage falls below this trip point.
WDI
The Watchdog Input takes an input from a microprocessor
and ensures that it periodically toggles the WDI pin,
otherwise the internal watchdog timer runs out and reset is
asserted. The internal Watchdog Timer is cleared whenever
the WDI input pin sees a rising or falling edge or the device
is manually reset.
C
POR
The C
POR
input pin lets users increase the Power On Reset
timeout delay (t
POR
) by connecting a capacitor between
C
POR
and ground. (See Figure 3)
V
THVMON
HYST
RESET
Hysteresis Voltage (Notes 4, 5)
3
mV
V
OL
Reset Output Voltage Low
V
DD
≥
3.3V, Sinking 0.5mA
V
DD
< 3.3V, Sinking 0.5mA
V
DD
≥
3.3V, Sourcing 0.4mA
V
DD
< 3.3V, Sourcing 0.4mA
0.05
0.40
V
0.05
0.40
V
V
OH
Reset Output Voltage High
V
DD
-0.6
V
DD
-0.6
V
DD
-0.4
V
DD
-0.4
60
V
V
t
RPD
t
POR
V
TH
to Reset Asserted Delay
POR Timeout Delay
μs
ISL88012, ISL88013, ISL88015
140
200
260
ms
ISL88011, ISL88014 with C
POR
= OPEN
200
250
ms
C
LOAD
MANUAL RESET
Load Capacitance on Reset Pins
5
pF
V
MR
t
MR
WATCHDOG TIMER (Note 6)
MR Input Voltage
0
100
mV
MR Minimum Pulse Width
1
μs
Start t
WDT
Startup Watchdog Timeout Period
t
WDT
Normal Watchdog Timeout Period
t
WDPS
WDI Minimum Pulse Width
V
IL
Watchdog Input Voltage Low
V
IH
Watchdog Input Voltage High
I
WDT
Watchdog Input Current
NOTES:
4. Applies to ISL88012
5. Applies to ISL88014 and ISL88015.
6. Applies to ISL88013 and ISL88015.
32
51
64
sec
1.0
1.6
2.0
sec
100
ns
0.3 x V
DD
V
0.85 x V
DD
V
100
nA
Electrical Specifications
Over the recommended operating conditions unless otherwise specified, R
PU
= 10k
Ω
.
(Continued)
PARAMETER
TEST CONDITIONS
SYMBOL
MIN
TYP
MAX
UNITS
ISL88011, ISL88012, ISL88013, ISL88014, ISL88015
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