參數(shù)資料
型號： ISL90840UAV2027Z
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計
英文描述： Quad Digitally Controlled Potentiometers (XDCP)
中文描述： QUAD 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20
封裝： ROHS COMPLIANT, TSSOP-20
文件頁數(shù)： 5/13頁
文件大?。?/td> 1085K
代理商： ISL90840UAV2027Z
5
FN8086.2
November 14, 2006
TC
R
(Note 17)
Resistance temperature coefficient
DCP register set between 20 hex and FF hex
±45
ppm/°C
Analog Specifications
Over recommended operating conditions unless otherwise stated.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 4)
MAX
UNIT
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 4)
MAX
UNIT
I
CC1
V
CC
supply current (volatile
write/read)
f
SCL
= 400kHz; SDA = Open; (for I
2
C, active,
read and write states)
V
CC
= +5.5V, I
2
C Interface in Standby State,
Temperature range from -40°C to 85°C
V
CC
= +5.5V, I
2
C Interface in Standby State,
Temperature range from -40°C to 105°C
V
CC
= +3.6V, I
2
C Interface in Standby State,
Temperature range from -40°C to 85°C
V
CC
= +3.6V, I
2
C Interface in Standby State,
Temperature range from -40°C to 105°C
1
mA
I
SB
V
CC
current (standby)
2
5
μA
2
8
μA
0.8
2
μA
0.8
5
μA
I
LkgDig
Leakage current, at pins A0, A1, A2,
SDA, and SCL
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 18)
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
1
μs
SERIAL INTERFACE SPECS
V
IL
A2, A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*V
CC
V
V
IH
A2, A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 18)
V
OL
(Note 18)
Cpin
(Note 18)
SDA and SCL input buffer hysteresis
0.05*
V
CC
0
V
SDA output buffer LOW voltage,
sinking 4mA
0.4
V
A2, A1, A0, SDA, and SCL pin
capacitance
10
pF
f
SCL
t
IN
SCL frequency
400
kHz
(Note 18)
t
AA
(Note 18)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of V
CC
, until
SDA exits the 30% to 70% of V
CC
window
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during the following START condition
900
ns
t
BUF
(Note 18)
Time the bus must be free before the
start of a new transmission
1300
ns
t
LOW
t
HIGH
t
SU:STA
Clock LOW time
Measured at the 30% of V
CC
crossing
Measured at the 70% of V
CC
crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V
CC
From SDA falling edge crossing 30% of V
CC
to SCL falling edge crossing 70% of V
CC
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of
V
CC
From SCL rising edge crossing 70% of V
CC
to SDA entering the 30% to 70% of V
CC
window
1300
ns
Clock HIGH time
600
ns
START condition setup time
600
ns
t
HD:STA
START condition hold time
600
ns
t
SU:DAT
Input data setup time
100
ns
t
HD:DAT
Input data hold time
0
ns
ISL90840
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