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參數(shù)資料
| 型號： | ISL90840UAV2027Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 0K |
| 描述： | IC POT XDCP QUAD LN LP 20-TSSOP |
| 標準包裝： | 75 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 溫度系數(shù)： | 標準值 ±45 ppm/°C |
| 存儲器類型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-TSSOP |
| 包裝： | 管件 |
5
FN8086.2
November 14, 2006
TCR
(Note 17)
Resistance temperature coefficient
DCP register set between 20 hex and FF hex
±45
ppm/°C
Analog Specifications
Over recommended operating conditions unless otherwise stated. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 4)
MAX
UNIT
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 4)
MAX
UNIT
ICC1
VCC supply current (volatile
write/read)
fSCL = 400kHz; SDA = Open; (for I
2C, active,
read and write states)
1mA
ISB
VCC current (standby)
VCC = +5.5V, I
2C Interface in Standby State,
Temperature range from -40°C to 85°C
25
A
VCC = +5.5V, I
2C Interface in Standby State,
Temperature range from -40°C to 105°C
28
A
VCC = +3.6V, I
2C Interface in Standby State,
Temperature range from -40°C to 85°C
0.8
2
A
VCC = +3.6V, I
2C Interface in Standby State,
Temperature range from -40°C to 105°C
0.8
5
A
ILkgDig
Leakage current, at pins A0, A1, A2,
SDA, and SCL
Voltage at pin from GND to VCC
-10
10
A
tDCP
(Note 18)
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
1s
SERIAL INTERFACE SPECS
VIL
A2, A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
V
VIH
A2, A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 18)
SDA and SCL input buffer hysteresis
0.05*
VCC
V
VOL
(Note 18)
SDA output buffer LOW voltage,
sinking 4mA
00.4
V
Cpin
(Note 18)
A2, A1, A0, SDA, and SCL pin
capacitance
10
pF
fSCL
SCL frequency
400
kHz
tIN
(Note 18)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
(Note 18)
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
(Note 18)
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START condition hold time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input data setup time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input data hold time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0ns
ISL90840
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