FN8094.1 February 8, 2006 SDA vs SCL Timing A0 and A1 Pin Timing tF (Note 15) SDA a" />
參數(shù)資料
型號(hào): ISL90841WIV1427Z
廠商: Intersil
文件頁(yè)數(shù): 8/12頁(yè)
文件大小: 0K
描述: IC XDCP 256-TAP 10KOHM TSSOP-14
標(biāo)準(zhǔn)包裝: 95
系列: XDCP™
接片: 256
電阻(歐姆): 10k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±45 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
5
FN8094.1
February 8, 2006
SDA vs SCL Timing
A0 and A1 Pin Timing
tF
(Note 15)
SDA and SCL fall time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb
(Note 15)
Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 15)
SDA and SCL bus pull-up resistor off-
chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1k
tSU:A
A1 and A0 setup time
Before START condition
600
ns
tHD:A
A1 and A0 hold time
After STOP condition
600
ns
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
tSU:STO
tDH
tHIGH
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF
tLOW
tBUF
tAA
tR
tHD:A
SCL
SDA IN
A0, A1
tSU:A
CLK 1
START
STOP
ISL90841
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