FN8096.1 January 16, 2006 tDCP (Note 8) DCP wiper response time SCL falling edge of last bit of D" />
參數(shù)資料
型號(hào)： ISL90842UIV1427Z-TK
廠商： Intersil
文件頁數(shù)： 5/10頁
文件大?。?/td> 0K
描述： IC POT DGTL QUAD 50K OHM 14TSSOP
產(chǎn)品培訓(xùn)模塊： Digitally Controlled Potentiometers
標(biāo)準(zhǔn)包裝： 1
系列： XDCP™
接片： 256
電阻（歐姆）： 50k
電路數(shù)： 4
溫度系數(shù)： 標(biāo)準(zhǔn)值 ±45 ppm/°C
存儲(chǔ)器類型： 易失
接口： I²C（設(shè)備位址）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1237 (CN2011-ZH PDF)
其它名稱： ISL90842UIV1427Z-TKDKR
4
FN8096.1
January 16, 2006
tDCP
(Note 8)
DCP wiper response time
SCL falling edge of last bit of DCP data byte
to wiper change
1s
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL input buffer
LOW voltage
-0.3
0.3*VCC
V
VIH
A1, A0, SDA, and SCL input buffer
HIGH voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 8)
SDA and SCL input buffer hysteresis
0.05*
VCC
V
VOL
(Note 8)
SDA output buffer LOW voltage,
sinking 4mA
00.4
V
Cpin
(Note 8)
A1, A0, SDA, and SCL pin
capacitance
10
pF
fSCL
SCL frequency
400
kHz
tIN
(Note 8)
Pulse width suppression time at SDA
and SCL inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
(Note 8)
SCL falling edge to SDA output data
valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
(Note 8)
Time the bus must be free before the
start of a new transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC
during the following START condition
1300
ns
tLOW
Clock LOW time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START condition setup time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START condition hold time
From SDA falling edge crossing 30% of VCC
to SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input data setup time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
tHD:DAT
Input data hold time
From SCL rising edge crossing 70% of VCC
to SDA entering the 30% to 70% of VCC
window
0ns
tSU:STO
STOP condition hold time
From SCL rising edge crossing 70% of VCC,
to SDA rising edge crossing 30% of VCC
600
ns
tHD:STO
STOP condition hold time for read, or
volatile only write
From SDA rising edge to SCL falling edge.
Both crossing 70% of VCC
600
ns
tDH
(Note 8)
Output data hold time
From SCL falling edge crossing 30% of VCC,
until SDA enters the 30% to 70% of VCC
window
0ns
tR
(Note 8)
SDA and SCL rise time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF
(Note 8)
SDA and SCL fall time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb (Note 8) Capacitive loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
(Note 8)
SDA and SCL bus pull-up resistor off-
chip
Maximum is determined by tR and tF
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1k
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNIT
ISL90842
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