FN8096.1 January 16, 2006 The ISL90842 responds with an ACK after recognition of a START condition followed by a valid Identification Byte, and " />
參數(shù)資料
型號(hào): ISL90842UIV1427Z
廠商: Intersil
文件頁數(shù): 9/10頁
文件大?。?/td> 0K
描述: IC DCP 256-TAP 50KOHM TSSOP-14
標(biāo)準(zhǔn)包裝: 95
系列: XDCP™
接片: 256
電阻(歐姆): 50k
電路數(shù): 4
溫度系數(shù): 標(biāo)準(zhǔn)值 ±45 ppm/°C
存儲(chǔ)器類型: 易失
接口: I²C(設(shè)備位址)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 管件
8
FN8096.1
January 16, 2006
The ISL90842 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again after successful receipt of an Address Byte. The
ISL90842 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation
A valid Identification Byte contains 01010 as the five MSBs,
and the following two bits matching the logic values present
at pins A1 and A0. The LSB is the Read/Write bit. Its value is
“1” for a Read operation, and “0” for a Write operation (See
Table 1).
TABLE 1. IDENTIFICATION BYTE FORMAT
01010
A1
A0
R/W
(MSB)
(LSB)
Logic values at pins A1, and A0 respectively
FIGURE 9. VALID DATA CHANGES, START, AND STOP CONDITIONS
FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 11. BYTE WRITE SEQUENCE
SDA
SCL
START
DATA
STOP
STABLE
CHANGE
DATA
STABLE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL90842
A
C
K
00
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 0 0
A0
A1
00 000
ISL90842
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