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參數(shù)資料
| 型號： | ISL90843UIU1027Z-TK |
| 廠商： | Intersil |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDCP 256-TAP 50OHM 10-MSOP |
| 標準包裝： | 1,000 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 4 |
| 存儲器類型： | 易失 |
| 接口： | I²C（設(shè)備位址） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
4
FN8095.2
March 29, 2006
VccRamp VCC Ramp Rate
0.2
V/ms
tD (Note 15) Power-Up Delay
VCC above Vpor, to DCP Initial Value Register recall
completed, and I2C Interface in Standby State.
3ms
SERIAL INTERFACE SPECS
VIL
A1, A0, SDA, and SCL Input
Buffer LOW Voltage
-0.3
0.3*VCC
V
VIH
A1, A0, SDA, and SCL Input
Buffer HIGH Voltage
0.7*VCC
VCC+0.3
V
Hysteresis
(Note 15)
SDA and SCL Input Buffer
Hysteresis
0.05*
VCC
V
VOL
(Note 15)
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin
(Note 15)
A1, A0, SDA, and SCL Pin
Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN
(Note 15)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is suppressed.
50
ns
tAA
(Note 15)
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of VCC, until SDA exits
the 30% to 70% of VCC window.
900
ns
tBUF
(Note 15)
Time the Bus Must be Free Before
the Start of a New Transmission
SDA crossing 70% of VCC during a STOP condition, to
SDA crossing 70% of VCC during the following START
condition.
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing.
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing.
600
ns
tSU:STA
START Condition Setup Time
SCL rising edge to SDA falling edge. Both crossing 70%
of VCC.
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to SCL
falling edge crossing 70% of VCC.
600
ns
tSU:DAT
Input Data Setup Time
From SDA exiting the 30% to 70% of VCC window, to
SCL rising edge crossing 30% of VCC.
100
ns
tHD:DAT
Input Data Hold Time
From SCL rising edge crossing 70% of VCC to SDA
entering the 30% to 70% of VCC window.
0ns
tSU:STO
STOP Condition Setup Time
From SCL rising edge crossing 70% of VCC, to SDA
rising edge crossing 30% of VCC.
600
ns
tHD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
From SDA rising edge to SCL falling edge. Both crossing
70% of VCC.
600
ns
tDH
(Note 15)
Output Data Hold Time
From SCL falling edge crossing 30% of VCC, until SDA
enters the 30% to 70% of VCC window.
0ns
tR
(Note 15)
SDA and SCL Rise Time
From 30% to 70% of VCC
20 +
0.1 * Cb
250
ns
tF
(Note 15)
SDA and SCL Fall Time
From 70% to 30% of VCC
20 +
0.1 * Cb
250
ns
Cb
(Note 15)
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
pF
Rpu
(Note 15)
SDA and SCL Bus Pull-Up
Resistor Off-Chip
Maximum is determined by tR and tF.
For Cb = 400pF, max is about 2~2.5k
.
For Cb = 40pF, max is about 15~20k
1k
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 1)
MAX
UNITS
ISL90843
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