4
FN8084.1
February 6, 2008
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
VCC Supply Current, Volatile
Write/read
fSCL = 400kHz; SDA = Open; (for I
2C, active,
read, and volatile write states only)
1mA
ICC2
VCC Supply Current, Nonvolatile
Write
fSCL = 400kHz; SDA = Open; (for I
2C, active,
nonvolatile write states only)
3mA
ISB
VCC Current, Standby
VCC = +5.5V, I
2C interface in standby state
5
A
VCC = +3.6V, I
2C interface in standby state
2
A
IV+
V+ Bias Current
V+ = 13.2V, VCC = +5.5V
1
A
ILkgDig
Leakage Current, at Pins SDA, SCL,
A0, and A1 Pins
Voltage at pin from GND to VCC
-10
10
A
tDCP
DCP Wiper Response Time
SCL falling edge of last bit of DCP data byte to
wiper change
1s
Vpor
Power-On Recall Voltage
VCC range at which memory recall occurs
1.5
1.8
2.6
V
VCCRamp
VCC Ramp Rate
0.2
V/ms
tD
Power-Up Delay
VCC above Vpor, to DCP initial value register
recall completed, and I2C Interface in standby
state
3ms
EEPROM SPECS
EEPROM Endurance
200,000
Cycles
EEPROM Retention
Temperature
≤ +75°C
50
Years
SERIAL INTERFACE SPECS
VIL
A0, A1, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*
VCC
V
VIH
A0, A1, SDA, and SCL Input Buffer
HIGH Voltage
0.7*
VCC
VCC+
0.3
V
Hysteresis
SDA and SCL Input Buffer Hysteresis
0.05*
VCC
V
VOL
SDA Output Buffer LOW Voltage,
Sinking 4mA
00.4
V
Cpin
A0, A1, SDA, and SCL Pin
Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed
50
ns
tAA
SCL Falling Edge to SDA Output Data
Valid
SCL falling edge crossing 30% of VCC, until
SDA exits the 30% to 70% of VCC window
900
ns
tBUF
Time the Bus Must be Free Before the
Start of a New Transmission
SDA crossing 70% of VCC during a STOP
condition, to SDA crossing 70% of VCC during
the following START condition
1300
ns
tLOW
Clock LOW Time
Measured at the 30% of VCC crossing
1300
ns
tHIGH
Clock HIGH Time
Measured at the 70% of VCC crossing
600
ns
tSU:STA
START Condition Set-up Time
SCL rising edge to SDA falling edge; both
crossing 70% of VCC
600
ns
tHD:STA
START Condition Hold Time
From SDA falling edge crossing 30% of VCC to
SCL falling edge crossing 70% of VCC
600
ns
tSU:DAT
Input Data Set-up Time
From SDA exiting the 30% to 70% of VCC
window, to SCL rising edge crossing 30% of
VCC
100
ns
ISL95311