參數(shù)資料
型號(hào)： ISL95810UIU8Z-T
廠商： INTERSIL CORP
元件分類： 數(shù)字電位計(jì)
英文描述： Single Digitally Controlled Potentiometer (XDCP)
中文描述： 50K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO8
封裝： ROHS COMPLIANT, PLASTIC, MO-187AA, MSOP-8
文件頁數(shù)： 4/13頁
文件大?。?/td> 1160K
代理商： ISL95810UIU8Z-T
4
FN8090.1
October 7, 2005
I
LkgDig
Leakage Current, at Pins SDA,
SCL, and WP Pins
Voltage at pin from GND to V
CC
-10
10
μA
t
DCP
(Note 13)
DCP Wiper Response Time
SCL falling edge of last bit of DCP Data Byte to
wiper change
1
μs
Vpor
Power-On Recall Voltage
Minimum V
CC
at which memory recall occurs
1.8
2.6
V
V
CC
Ramp
t
D
(Note 13)
V
CC
Ramp Rate
Power-Up Delay
0.2
V/ms
V
CC
above Vpor, to DCP Initial Value Register
recall completed, and I
2
C Interface in standby state
3
ms
EEPROM SPECIFICATIONS
EEPROM Endurance
200,000
Cycles
EEPROM Retention
Temperature
≤
75°C
50
Years
SERIAL INTERFACE SPECIFICATIONS
V
IL
WP, SDA, and SCL Input Buffer
LOW Voltage
-0.3
0.3*V
CC
V
V
IH
WP, SDA, and SCL Input Buffer
HIGH Voltage
0.7*V
CC
V
CC
+0.3
V
Hysteresis
(Note 13) SDA and SCL Input Buffer
Hysteresis
V
OL
(Note 13)
SDA Output Buffer LOW Voltage,
Sinking 4mA
Cpin
(Note 13)
WP, SDA, and SCL Pin
Capacitance
0.05*
V
CC
0
V
0.4
V
10
pF
f
SCL
SCL Frequency
400
kHz
t
IN
(Note 13)
Pulse Width Suppression Time at
SDA and SCL Inputs
Any pulse narrower than the max spec is
suppressed.
50
ns
t
AA
(Note 13)
SCL Falling Edge to SDA Output
Data Valid
SCL falling edge crossing 30% of V
CC
, until SDA
exits the 30% to 70% of V
CC
window.
SDA crossing 70% of V
CC
during a STOP
condition, to SDA crossing 70% of V
CC
during
the following START condition.
900
ns
t
BUF
(Note 13)
Time the Bus Must be Free Before
the Start of a New Transmission
1300
ns
t
LOW
t
HIGH
t
SU:STA
Clock LOW Time
Measured at the 30% of V
CC
crossing.
Measured at the 70% of V
CC
crossing.
SCL rising edge to SDA falling edge. Both
crossing 70% of V
CC
.
From SDA falling edge crossing 30% of V
CC
to
SCL falling edge crossing 70% of V
CC
.
From SDA exiting the 30% to 70% of V
CC
window, to SCL rising edge crossing 30% of V
CC
From SCL rising edge crossing 70% of V
CC
to
SDA entering the 30% to 70% of V
CC
window.
From SCL rising edge crossing 70% of V
CC
, to
SDA rising edge crossing 30% of V
CC
.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
CC
.
From SCL falling edge crossing 30% of V
CC
, until
SDA enters the 30% to 70% of V
CC
window.
From 30% to 70% of V
CC
1300
ns
Clock HIGH Time
600
ns
START Condition Setup Time
600
ns
t
HD:STA
START Condition Hold Time
600
ns
t
SU:DAT
Input Data Setup Time
100
ns
t
HD:DAT
Input Data Hold Time
0
ns
t
SU:STO
STOP Condition Setup Time
600
ns
t
HD:STO
STOP Condition Hold Time for
Read, or Volatile Only Write
600
ns
t
HD:STO:NV
STOP Condition Hold Time for
Non-Volatile Write
2
μs
t
DH
(Note 13)
Output Data Hold Time
0
ns
t
R
(Note 13)
SDA and SCL Rise Time
20 +
0.1 * Cb
250
ns
Operating Specifications
Over the recommended operating conditions unless otherwise specified.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNITS
ISL95810
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