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參數(shù)資料
型號(hào): ISL95810UIU8Z
廠商: Intersil
文件頁數(shù): 12/13頁
文件大小: 0K
描述: IC XDCP SGL 256-TAP 50KOHM 8MSOP
標(biāo)準(zhǔn)包裝: 80
系列: XDCP™
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準(zhǔn)值 ±45 ppm/°C
存儲(chǔ)器類型: 非易失
接口: I²C
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-TSSOP,8-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 8-MSOP
包裝: 管件
8
FN8090.2
September 19, 2006
Principles of Operation
The ISL95810 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory, and a I2C
serial interface providing direct communication between a
host and the potentiometer and memory.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of the
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). The DCP has its own WR.
When the WR of the DCP contains all zeroes (WR<7:0>:
00h), its wiper terminal (RW) is closest to its “Low” terminal
(RL). When the WR of the DCP contains all ones (WR<7:0>:
FFh), its wiper terminal (RW) is closest to its “High” terminal
(RH). As the value of the WR increases from all zeroes (00h)
to all ones (255 decimal), the wiper moves monotonically
from the position closest to RL to the closest to RH. At the
same time, the resistance between RW and RL increases
monotonically, while the resistance between RH and RW
decreases monotonically.
While the ISL95810 is being powered up, The WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. Soon after the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the ISL95810 reads the value stored in non-volatile
Initial Value Registers (IVRs) and loads it into the WR.
The WR and IVR can be read or written directly using the
I2C serial interface as described in the following sections.
Memory Description
The ISL95810 volatile and non-volatile registers are
accessed by I2C interface operations at addresses 0 and 2
decimal. The non-volatile byte at addresses 0 contains the
initial value loaded at power-up into the volatile Wiper
Register (WR) of the DCP. The byte at address 1 is
reserved; the user should not write to it, and its value should
be ignored if read.
The volatile WR, and the non-volatile Initial Value Register
(IVR) of the DCP are accessed with the same Address Byte,
set to 00 hex in both cases.
A volatile byte at address 2 decimal, controls what byte is
read or written when accessing DCP registers: the WR, the
IVR, or both.
When the byte at address 2 is all zeroes, which is the default
at power-up:
A read operation to addresses 0 outputs the value of the
non-volatile IVR.
A write operation to addresses 0 writes the same value to
the WR and IVR of the corresponding DCP.
When the byte at address 2 is 80h (128 decimal):
A read operation to addresses 0 outputs the value of the
volatile WR.
A write operation to addresses 0 only writes to the
corresponding volatile WR.
It is not possible to write to an IVR without writing the same
value to its corresponding WR.
00h and 80h are the only values that should be written to
address 2. All other values are reserved and must not be
written to address 2.
FIGURE 13. MIDSCALE GLITCH, CODE 80h to 7Fh (WIPER 0)
FIGURE 14. LARGE SIGNAL SETTLING TIME
Typical Performance Curves (Continued)
Wiper Movement Mid Point
From 80h to 7fh
Signal at Wiper (Wiper Unloaded)
SCL
Signal at Wiper
(Wiper Unloaded Movement
From ffh to 00h)
ISL95810
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