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參數(shù)資料
| 型號(hào)： | ISL96017 |
| 廠商： | Intersil Corporation |
| 英文描述： | 128-Tap DCP, 16kbit EEPROM, and I2C Serial Interface(128抽頭DCP, 16kbit EEPROM, I2C串行接口) |
| 中文描述： | 128抽頭磷酸氫鈣，16kbit EEPROM和I2C串行接口（128抽頭應(yīng)課稅品許可證，16kbit的EEPROM和I2C串行接口） |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大小： | 326K |
| 代理商： | ISL96017 |
5
FN8243.1
April 17, 2006
I
2
C Timing Diagram
t
HD:STO
STOP Condition Hold Time
From SDA rising edge to SCL falling edge. Both
crossing 70% of VDD
600
ns
t
DH
Output Data Hold Time
From SCL falling edge crossing 30% of VDD,
until SDA enters the 30% to 70% of VDD
window
0
ns
t
R
SDA and SCL Rise Time
From 30% to 70% of VDD
20+
0.1*Cb
250
ns
t
F
SDA and SCL Fall Time
From 70% to 30% of VDD
20+
0.1*Cb
250
ns
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
400
pF
Rpu
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Maximum is determined by t
R
and t
F
For Cb = 400pF, max is about 2~2.5k
For Cb = 40pF, max is about 15~20k
1
k
t
SU:WP
WP Setup Time
Before START condition
600
ns
t
HD:WP
WP Hold Time
After STOP condition
600
ns
NOTES:
2. Typical values are for T
A
= 25°C and V
DD
= 3.3V.
3. LSB = (V(RW)
127
– V(RW)
0
)/127. V(RW)
127
and V(RW)
0
are the voltage at pin RW for the DCP Register set to 7F hex and 00 hex respectively.
4. FSerror = (V(RW)
127
– VDD)/LSB
5. ZSerror = V(RW)
0
/LSB
6. DNL = [(V(RW)
i
– V(RW)
i-1
)/LSB] – 1, for i from 1 to 127. i is the DCP Register setting.
7. INL = [V(RW)
i
– i * LSB – V(RW)
0
]/LSB, for I = 1 to 127.
6
C
8.
for i = 16 to 111, and T = -40°C to 85°C
9. MI = (R
0
– R
127
)/127. MI is minimum increment. R
0
and R
127
are the resistances between RH and RW with the DCP Register set to 00 hex and
7F hex, respectively.
10. RDNL = (R
i
– R
i-1
)/MI – 1, for i from 1 to 111. i is the DCP Register setting.
11. RINL = [R
i
– (MI * i) – R
127
]/MI, for i from 1 to 111.
12.
; for i = 1 to 111, and T = -40°C to 85°C
13. t
WC
is the minimum cycle time to be allowed for any non-volatile Write by the user, unless Acknowledge Polling is used. It is the time from a
valid STOP condition at the end of a Write sequence of a I
2
C serial interface Write operation, to the end of the self-timed internal non-volatile
write cycle.
14. Parameter is not 100% tested.
Electrical Specifications
Over recommended operating conditions unless otherwise stated. All voltages with respect to GND.
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(Note 1)
MAX
UNIT
TC
V
+
Min V RW
]
i
)
i
)
2
-----------------------------------------------–
-----------------
×
=
TC
R
(
Min Ri
Min Ri
(
)
–
]
)
]
2
--------------------------+
C
10
6
×
------------------
×
=
t
SU:STO
t
DH
t
HIGH
t
SU:STA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
t
F
t
LOW
t
BUF
t
AA
t
R
ISL96017
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