參數(shù)資料
型號： ISL98001CQZ-140
廠商： INTERSIL CORP
元件分類： 消費(fèi)家電
英文描述： Triple Video Digitizer with Digital PLL
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP128
封裝： 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128
文件頁數(shù)： 26/29頁
文件大?。?/td> 470K
代理商： ISL98001CQZ-140
26
FN6148.0
October 25, 2005
To allow input monitoring and mode detection during power-
down, the following blocks remain active:
Serial interface (including the crystal oscillator) to enable
register read/write activity
Activity and polarity detect functions (registers 0x01 and
0x02)
The HSYNC
OUT
and VSYNC
OUT
pins (for mode
detection)
Initialization
The ISL98001 initializes with default register settings for an
AC-coupled, RGB input on the VGA1 channel, with a 24-bit
output.
Reset
The ISL98001 has a Power On Reset (POR) function that
resets the chip to its default state when power is initially
applied, including resetting all the registers to their default
settings as described in the Register Listing. The external
RESET pin duplicates the reset function of the POR without
having to cycle the power supplies. The RESET pin does not
need to be used in normal operation and can be tied high.
ISL98001 Serial Communication
Overview
The ISL98001 uses a 2-wire serial bus for communication
with its host. SCL is the Serial Clock line, driven by the host,
and SDA is the Serial Data line, which can be driven by all
devices on the bus. SDA is open drain to allow multiple
devices to share the same bus simultaneously.
Communication is accomplished in three steps:
1)
The Host selects the ISL98001 it wishes to communicate
with.
2)
The Host writes the initial ISL98001 Configuration
Register address it wishes to write to or read from.
3)
The Host writes to or reads from the ISL98001’s
Configuration Register. The ISL98001’s internal address
pointer auto increments, so to read registers 0x00 through
0x1B, for example, one would write 0x00 in step 2, then
repeat step three 28 times, with each read returning the
next register value.
The ISL98001 has a 7-bit address on the serial bus. The
upper 6-bits are permanently set to 100110, with the lower
bit determined by the state of pin 48. This allows two
ISL98001s to be independently controlled while sharing the
same bus.
The bus is nominally inactive, with SDA and SCL high.
Communication begins when the host issues a START
command by taking SDA low while SCL is high (Figure 9).
The ISL98001 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command
until this condition has been met. The host then transmits the
7-bit serial address plus a R/W bit, indicating if the next
transaction will be a Read (R/W = 1) or a Write (R/W = 0). If
the address transmitted matches that of any device on the
bus, that device must respond with an ACKNOWLEDGE
(Figure 10).
Once the serial address has been transmitted and
acknowledged, one or more bytes of information can be
written to or read from the slave. Communication with the
selected device in the selected direction (read or write) is
ended by a STOP command, where SDA rises while SCL is
high (Figure 9), or a second START command, which is
commonly used to reverse data direction without
relinquishing the bus.
Data on the serial bus must be valid for the entire time SCL
is high (Figure 11). To achieve this, data being written to the
ISL98001 is latched on a delayed version of the rising edge
of SCL. SCL is delayed and deglitched inside the ISL98001
for three crystal clock periods (120ns for a 25MHz crystal) to
eliminate spurious clock pulses that could disrupt serial
communication.
When the contents of the ISL98001 are being read, the SDA
line is updated after the falling edge of SCL, delayed and
deglitched in the same manner.
Configuration Register Write
Figure 12 shows two views of the steps necessary to write
one or more words to the Configuration Register.
Configuration Register Read
Figure 13 shows two views of the steps necessary to read
one or more words from the Configuration Register.
SCL
SDA
Start
Stop
FIGURE 9. VALID START AND STOP CONDITIONS
ISL98001
相關(guān)PDF資料
PDF描述
ISL98001CQZ-210 Triple Video Digitizer with Digital PLL
ISL98001CQZ-240 Triple Video Digitizer with Digital PLL
ISL98001CQZ-275 Triple Video Digitizer with Digital PLL
ISL98001 Triple Video Digitizer with Digital PLL
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