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參數(shù)資料
| 型號(hào)： | ISL98001CQZ-275 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Triple Video Digitizer with Digital PLL |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP128 |
| 封裝： | 14 x 20 MM, ROHS COMPLIANT, PLASTIC, MS-022, MQFP-128 |
| 文件頁(yè)數(shù)： | 14/29頁(yè) |
| 文件大小： | 470K |
| 代理商： | ISL98001CQZ-275 |
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14
FN6148.0
October 25, 2005
0x09
Red Offset (0x80)
7:0
Red Offset
ABLC enabled: digital offset control. A 1LSB change
in this register will shift the ADC output by 1 LSB.
ABLC disabled: analog offset control. These bits go
to the upper 8-bits of the 10-bit offset DAC. A 1LSB
change in this register will shift the ADC output
approximately 1 LSB (Offset DAC range = 0) or
0.5LSBs (Offset DAC range = 1).
0x00 = min DAC value or -0x80 digital offset,
0x80 = mid DAC value or 0x00 digital offset,
0xFF = max DAC value or +0x7F digital offset
0x0A
Green Offset (0x80)
7:0
Green Offset
0x0B
Blue Offset (0x80)
7:0
Blue Offset
0x0C
Offset DAC Configuration (0x00)
0
Offset DAC Range
0: ± ADC fullscale (1 DAC LSB ~ 1 ADC LSB)
1: ± ADC fullscale (1 DAC LSB ~ ADC LSB)
1
Reserved
Set to 0.
3:2
Red Offset DAC
LSBs
These bits are the LSBs necessary for 10-bit manual
offset DAC control.
Combine with their respective MSBs in registers
0x09, 0x0A, and 0x0B to achieve 10-bit offset DAC
control.
5:4
Green Offset DAC
LSBs
7:6
Blue Offset DAC
LSBs
0x0D
AFE Bandwidth (0x2E)
0
Unused
Value doesn’t matter
3:1
AFE BW
3dB point for AFE lowpass filter
000b: 100MHz
111b: 780MHz (default)
7:4
Peaking
0x0: Peaking off
0x1: Moderate peaking
0x2: Maximum recommended peaking (default)
Values above 2 are not recommended.
0x0E
PLL Htotal MSB (0x03)
5:0
PLL Htotal MSB
14-bit HTOTAL (number of active pixels) value
The minimum HTOTAL value supported is 0x200.
HTOTAL to PLL is updated on LSB write only.
0x0F
PLL Htotal LSB (0x20)
7:0
PLL Htotal LSB
0x10
PLL Sampling Phase (0x00)
5:0
PLL Sampling Phase Used to control the phase of the ADC’s sample point
relative to the period of a pixel. Adjust to obtain
optimum image quality. One step = 5.625° (1.56% of
pixel period).
0x11
PLL Pre-coast (0x04)
7:0
Pre-coast
Number of lines the PLL will coast prior to the start of
VSYNC.
0x12
PLL Post-coast (0x04)
7:0
Post-coast
Number of lines the PLL will coast after the end of
VSYNC.
Register Listing
(Continued)
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
ISL98001
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