參數資料
型號: ISP1130DL
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Universal Serial Bus compound hub with integrated keyboard controller
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝: PLASTIC, SSOP-56
文件頁數: 37/68頁
文件大小: 1786K
代理商: ISP1130DL
Philips Semiconductors
ISP1130
USB compound hub with keyboard controller
Objective specification
Rev. 01 — 23 March 2000
37 of 68
9397 750 06895
Philips Electronics N.V. 2000. All rights reserved.
10.3.2
Power Control register (PCON)
10.3.3
USB Control register (USBCON)
Table 50: Register bank selection
RS1
RS0
0
0
0
1
1
0
1
1
Register bank
0
1
2
3
Address range (Hex)
00 to 07
08 to 0F
10 to 17
18 to 1F
Table 51: PCON register: bit allocation
Bit
7
Symbol
-
Reset
0
Access
R/W
6
-
0
5
-
0
4
3
2
1
0
WLE
0
R/W
GF1
0
R/W
GF0
0
R/W
PD
0
R/W
IDL
0
R/W
R/W
R/W
Table 52: PCON register: bit description
Bit
Symbol
7 to 5
-
4
WLE
Description
reserved
Watchdog Load Enable. Writing a logic 1 enables writing to the
watchdog timer register and starts the watchdog timer for the first
time. A logic 0 disables writing to the watchdog timer register.
The watchdog timer can be stopped by writing 55H to the
WDTKEY register (see
Table 70
) or by a hardware reset.
General purpose flag set or reset by software.
General purpose flag set or reset by software.
Writing a logic 1 activates Power-down mode and switches off the
clock. When the microcontroller wakes up from Power-down mode
this bit is cleared to logic 0.
Writing a logic 1 activates Idle mode, switching off the normal clock
and turning on the sleep clock. A reset or interrupt returns the
microcontroller from Idle to normal mode and clears this bit to
logic 0.
3
2
1
GF1
GF0
PD
0
IDL
Table 53: USBCON register: bit allocation
Bit
7
Symbol
Self
Powered
Reset
0
Access
W
6
5
4
3
2
1
0
Enable
SYNCLK
1
W
Disable
KBDMatrix
1
W
GL-MEMSEL
Selection
1
W
Enable
OverCurrent
1
W
AnalogOC
Disable
1
W
Soft
Connect_N
1
W
Suspend
Clock
0
W
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