參數(shù)資料
型號: ISP1160BD/01,118
廠商: ST-ERICSSON
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 68/88頁
文件大?。?/td> 394K
代理商: ISP1160BD/01,118
Philips Semiconductors
ISP1160
Embedded USB Host Controller
Product data
Rev. 05 — 24 December 2004
70 of 88
9397 750 13963
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
13. Power-on reset (POR)
When VCC is directly connected to the RESET_N pin, the internal pulse width (tPORP)
will be typically (600 ns to 1000 ns)
+ X, when V
CC is 3.3 V. The time X depends on
how fast VCC is rising with respect to Vtrip (2.03 V). The time X is decided by the
external power supply circuit.
To give a better view of the functionality, Figure 33 shows a possible curve of
VCC(POR) with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, <11 s), the
internal POR pulse will not react and will remain LOW. The internal POR starts with a
1 at t0. At t1, the detector will see the passing of the trip level and a delay element will
add another tPORP before it drops to 0.
The internal POR pulse will be generated whenever VCC(POR) drops below Vtrip for
more than 11
s.
Even if VCC is 5.0 V, Vtrip still remains at 2.03 V. This is because the 5 V tolerant pads
and on-chip voltage regulator ensure that 3.3 V is going to the internal POR circuitry
by clipping the voltage above 3.3 V.
The RESET_N pin can be either connected to VCC (using the internal POR circuit) or
externally controlled (by the microprocessor, ASIC, and so on). Figure 34 shows the
availability of the clock with respect to the external POR.
(1) PORP = power-on reset pulse.
Fig 33. Internal POR timing.
Stable external clock is available at A.
Fig 34. Clock with respect to the external POR.
004aaa389
VBAT(POR)
t0
t1
t2
t3
t4
t5
Vtrip
t
PORP
PORP(1)
t
PORP
POR
EXTERNAL CLOCK
A
004aaa365
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