參數(shù)資料
型號： ISP1581
廠商： NXP Semiconductors N.V.
英文描述： Universal Serial Bus 2.0 high-speed interface device
中文描述： 通用串行總線2.0高速接口設(shè)備
文件頁數(shù)： 54/73頁
文件大?。?/td> 1819K
代理商： ISP1581
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
54 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
12.4 DMA timing
12.4.1
PIO mode
General
T
cy(RW)
t
AVLL
t
I1VLL
t
LLI2L
t
I2HI1X
read/write cycle time
address set-up time before ALE LOW
R/W set-up time before ALE LOW
ALE LOW to DS LOW delay
R/W hold time after DS HIGH
60
3
3
5
5
-
-
-
-
-
ns
ns
ns
ns
ns
Table 83: Parallel I/O timing parameters: multiplexed address/data bus
…continued
Symbol
Parameter
Min
Max
Unit
(1) The device address consists of signals CS1, CS0, DA2, DA1 and DA0.
(2) The data bus width depends on the PIO access command used. Task File register access uses 8 bits (DATA[7:0]), except
for Task File register 1F0 which uses 16 bits (DATA[15:0]). DMA commands 04H and 05H also use a 16-bit data bus.
(3) The device can negate IORDY to extend the PIO cycle with wait states. The host determines whether or not to extend the
current cycle after t
su4
following the assertion of DIOR or DIOW. The following three cases are distinguished:
a) Device keeps IORDY released (high-impedance): no wait state is generated.
b) Device negates IORDY during t
su4
, but re-asserts IORDY before t
su4
expires: no wait state is generated.
c) Device negates IORDY during t
su4
and keeps IORDY negated for at least 5 ns after t
su4
expires: a wait state is
generated. The cycle is completed as soon as IORDY is re-asserted. For extended read cycles (DIOR asserted), the
read data on lines DATAn must be valid at t
d1
before IORDY is asserted.
(4) DIOR and DIOW have a programmable polarity: shown here as active LOW signals.
Fig 13. PIO mode timing.
HIGH
(write) DATA[7:0]
(2)
(read) DATA[7:0]
(2)
device
(1)
address
valid
DIOR, DIOW
(4)
IORDY
(3a)
IORDY
(3b)
IORDY
(3c)
tw1
tw2
th1
tsu1
tsu2
tsu5
tsu4
tsu4
tw3
th2
tsu3
td2
th3
(min)
Tcy1
MGT499
相關(guān)PDF資料
PDF描述
ISP1581BD Universal Serial Bus 2.0 high-speed interface device
ISP1582 Hi-Speed Universal Serial Bus peripheral controller
ISP1582BS Hi-Speed Universal Serial Bus peripheral controller
ISP1583 Hi-Speed Universal Serial Bus peripheral controller
ISP1583BS Hi-Speed Universal Serial Bus peripheral controller
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