參數(shù)資料
型號: ISP1581BD
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Universal Serial Bus 2.0 high-speed interface device
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封裝: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件頁數(shù): 33/73頁
文件大小: 1819K
代理商: ISP1581BD
Philips Semiconductors
ISP1581
USB 2.0 HS interface device
Objective specification
Rev. 02 — 23 October 2000
33 of 73
9397 750 07648
Philips Electronics N.V. 2000. All rights reserved.
In 8-bit bus mode, the 16-bit Task File register 1F0 requires 2 consecutive write/read
accesses before the proper PIO write/read is generated on the IDE interface. The first
byte is always the lower byte (LSB). Other task file registers can be accessed directly.
Writing to Task File registers can be done in any order except for Task File register
1F7, which must be written last.
1F7
3F6
3F7
H
L
L
L
H
H
H
H
H
H
H
H
H
L
H
Table 42: ATAPI peripheral register addressing
…continued
Task file
CS1
CS0
DA2
DA1
DA0
Table 43: Task File register 1F0 (address: 40H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = L.
Bit
7
Symbol
Reset
Bus reset
Access
6
5
4
3
2
1
0
data (ATA or ATAPI)
00H
00H
R/W
Table 44: Task File register 1F1 (address: 48H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = L, DA0 = H.
Bit
7
Symbol
Reset
Bus reset
Access
6
5
4
3
2
1
0
error/feature (ATA or ATAPI)
00H
00H
R/W
Table 45: Task File register 1F2 (address: 49H): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = L.
Bit
7
Symbol
Reset
Bus reset
Access
6
5
4
3
2
1
0
sector count (ATA) or interrupt reason (ATAPI)
00H
00H
R/W
Table 46: Task File register 1F3 (address: 4AH): bit allocation
CS1 = H, CS0 = L, DA2 = L, DA1 = H, DA0 = H.
Bit
7
Symbol
Reset
Bus reset
Access
6
5
4
3
2
1
0
sector number/LBA[7:0] (ATA), reserved (ATAPI)
00H
00H
R/W
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