Specifications ispLSI 2032E
6
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-135
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030B/2032E
1
tsu2 + tco1
(
)
-110
MIN.
MAX.
DESCRIPTION
#
2
4
PARAMETER
A1
Data Propagation Delay, 4PT Bypass, ORP Bypass
–
7.5
–
10.0
ns
tpd2
A2
Data Propagation Delay
–
ns
fmax
A3
Clock Frequency with Internal Feedback3
137
–
111
–
MHz
fmax (Ext.)
–4
Clock Frequency with External Feedback
–
MHz
fmax (Tog.)
–5
Clock Frequency, Max. Toggle
–
MHz
tsu1
–6
GLB Register Setup Time before Clock, 4 PT Bypass
–
ns
tco1
A7
GLB Register Clock to Output Delay, ORP Bypass
–
ns
th1
–8
GLB Register Hold Time after Clock, 4 PT Bypass
0.0
–
ns
tsu2
–9
GLB Register Setup Time before Clock
5.5
–
ns
tco2
–10 GLB Register Clock to Output Delay
–
ns
th2
–11 GLB Register Hold Time after Clock
0.0
–
ns
tr1
A12 External Reset Pin to Output Delay, ORP Bypass
–
ns
trw1
–13 External Reset Pulse Duration
5.0
–
ns
tptoeen
B14 Input to Output Enable
–
ns
tptoedis
C15 Input to Output Disable
–
ns
tgoeen
B16 Global OE Output Enable
–
ns
tgoedis
C17 Global OE Output Disable
–
ns
twh
–18 External Synchronous Clock Pulse Duration, High
3.0
–
ns
twl
–19 External Synchronous Clock Pulse Duration, Low
3.0
–
ns
100
167
4.0
4.5
–
5.5
–
9.0
–
12.0
6.0
10.0
77.0
125
5.5
0.0
7.5
0.0
6.5
4.0
13.0
5.5
6.5
12.5
14.5
7.0