Specifications ispLSI 2096/A 8 USE ispLSI 2096E FOR NEW DESIGNS Power Consumption Power consumption in the ispLSI 2096 and 2096A de- vices depe" />
參數(shù)資料
型號: ISPLSI 2096A-80LTN128I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
描述: IC PLD ISP 96I/O 15NS 128TQFP
標準包裝: 90
系列: ispLSI® 2000A
可編程類型: 系統(tǒng)內可編程
最大延遲時間 tpd(1): 15.0ns
電壓電源 - 內部: 4.5 V ~ 5.5 V
邏輯元件/邏輯塊數(shù)目: 24
宏單元數(shù): 96
門數(shù): 4000
輸入/輸出數(shù): 96
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應商設備封裝: 128-TQFP(14x14)
包裝: 托盤
其它名稱: ISPLSI2096A-80LTN128I
Specifications ispLSI 2096/A
8
USE
ispLSI
2096E
FOR
NEW
DESIGNS
Power Consumption
Power consumption in the ispLSI 2096 and 2096A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
50
150
250
0
20
40
60
80
100 120 140
fmax (MHz)
I CC
(mA)
Notes: Configuration of six 16-bit counters
Typical current at 5V, 25°C
ispLSI 2096/A
200
100
0127/2096
ICC can be estimated for the ispLSI 2096/A using the following equation:
ICC(mA) = 20 + (# of PTs * 0.67) + (# of nets * Max freq * 0.011)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
300
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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ISPLSI2096E100LQ128 制造商:LATTICE 功能描述:New
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