Specifications ispLSI 5256VA 14 Internal Timing Parameters1 Over Recommended Operating Condition" />
參數(shù)資料
型號: ISPLSI 5256VA-100LQ208
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 6/27頁
文件大小: 0K
描述: IC PLD ISP 192I/O 10NS 208PQFP
標準包裝: 24
系列: ispLSI® 5000VA
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 3 V ~ 3.6 V
邏輯元件/邏輯塊數(shù)目: 8
宏單元數(shù): 256
門數(shù): 12000
輸入/輸出數(shù): 144
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: ISPLSI5256VA-100LQ208
Specifications ispLSI 5256VA
14
Internal Timing Parameters1
Over Recommended Operating Conditions
I/O Buffer
tidcom
22
Input Pad and Buffer, Combinatorial Input
0.7
0.9
1.4
ns
tidreg
23
Input Pad and Buffer, Registered Input
4.7
6.6
9.7
ns
todcom
24
Output Pad and Buffer, Combinatorial Output
1.3
1.7
2.6
ns
todreg
25
Output Pad and Buffer, Registered Output
1.8
2.8
4.6
ns
todz
26
Output Buffer Enable/Disable
1.3
1.7
2.6
ns
tslf
27
Slew Rate Adder, Fast Slew
–0–0–0
ns
tsls
28
Slew Rate Adder, Slow Slew
7.5
10
15
ns
tslfd
29
Programmable Delay Adder, Fast Slew
0.5
0.7
1
ns
tslsd
30
Programmable Delay Adder, Slow Slew
8
10.7
16
ns
GLB/Macrocell Delay Register
tmbp
31
Macrocell Register/Latch Bypass
–0–0–0
ns
tmlat
32
Macrocell Latch Delay
1
1.4
2
ns
tmco
33
Macrocell Register/Latch Clock to Output
–1–1–1
ns
tmsu
34
Macrocell Register/Latch Setup Time
1
1.1
1.7
ns
tmh
35
Macrocell Register/Latch Hold Time
2.5
3.9
5.3
ns
tmsuce
36
Macrocell Register/Latch CLKEN Setup Time
1
1.4
2
ns
tmhce
37
Macrocell Register/Latch CLKEN Hold Time
1
1.4
2
ns
tmrst
38
Macrocell Register/Latch Set/Reset Time
1
1.4
2
ns
tftog
39
Toggle Flip-Flop Feedback
1
1.3
2
ns
AND Array
tandhs
40
AND Array, High Speed Mode
–3–4–6
ns
tandlp
41
AND Array, Low Power Mode
5
6.6
10
ns
PTSA
t5ptcom
42
5 Product Term Bypass, Combinatorial
1
1.4
2
ns
t5ptreg
43
5 Product Term Bypass, Registered
1
1.7
2.3
ns
t5ptxcom
44
5 Product Term XOR, Combinatorial
2.5
3.6
5
ns
t5ptxreg
45
5 Product Term XOR, Registered
1.5
2.2
3.3
ns
tptsacom
46
Product Term Sharing Array, Combinatorial
3
4.1
6
ns
tptsareg
47
Product Term Sharing Array, Registered
2.0
2.7
4.3
ns
PTSA Controls
tpck
48
Product Term Clock Delay
0.5
0.7
1
ns
tpcken
49
Product Term CLKEN Delay
1
1.4
2
ns
tscken
50
Shared Product Term CLKEN Delay
1
1.4
2
ns
tsck
51
Shared Product Term Clock Delay
0.5
0.7
1
ns
tptsacken
52
Product Term Sharing Array CLKEN Delay
2.0
2.4
4
ns
tsrst
53
Shared Product Term Set/Reset Delay
2.5
3.4
5
ns
tprst
54
Product Term Set/Reset Delay
1.5
–2–3
ns
tpoe
55
Product Term Output Enable/Disable
2.5
3.4
5
ns
tgpoe
56
Global PT Output Enable/Disable
11.5
15.4
17
ns
-125
-100
-70
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
PARAM
#2
DESCRIPTION
1. Internal Timing Parameters are not tested and are for reference only.
Timing Rev. 4.0
2. Refer to Timing Model in this data sheet for further details.
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ISPLSI5256VA-100LQ208 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI5256VA-125LB208 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI5256VA-125LB272 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
ISPLSI5256VA125LQ208 制造商:Lattice 功能描述:_
ISPLSI5256VA-125LQ208 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100