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參數(shù)資料
| 型號(hào)： | ISPLSI 5512VA-70LB272 |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 22/28頁 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 288I/O 15NS 272BGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | ispLSI® 5000VA |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 邏輯元件/邏輯塊數(shù)目： | 16 |
| 宏單元數(shù)： | 512 |
| 門數(shù)： | 24000 |
| 輸入/輸出數(shù)： | 192 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 272-BBGA |
| 供應(yīng)商設(shè)備封裝： | 272-BGA（27x27） |
| 包裝： | 托盤 |
| 其它名稱： | ISPLSI5512VA-70LB272 |
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Specifications ispLSI 5512VA
3
ispLSI 5000V Description (Continued)
five extra product terms are used for shared GLB con-
trols, set, reset, clock, clock enable and output enable.
The 32 registered macrocells in the GLB are driven by the
32 outputs from the PTSA or the PTSA bypass. Each
macrocell contains a programmable XOR gate, a pro-
grammable register/latch/toggle flip-flop and the
necessary clocks and control logic to allow combinatorial
or registered operation. The macrocells each have two
outputs, which can be fed back through the Global
Routing Pool. This dual output capability from the
macrocell allows efficient use of the hardware resources.
One output can be a registered function for example,
while the other output can be an unrelated combinatorial
function. A direct register input from the I/O pad facilitates
efficient use of this feature to construct high-speed input
registers.
Macrocell registers can be clocked from one of several
global or product term clocks available on the device. A
global and product term clock enable is also provided,
eliminating the need to gate the clock to the macrocell
registers. Reset and preset for the macrocell register is
provided from both global and product term signals. The
macrocell register can be programmed to operate as a D-
type register, a D-type latch or a T-type flip flop.
The 32 outputs from the GLB can drive both the Global
Routing Pool and the device I/O cells. The Global Routing
Pool contains one line from each macrocell output and
one line from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/
2.5V compatible levels. The output driver can source
4mA and sink 8mA in 3.3V mode. The output drivers have
a separate VCCIO reference input which is independent
of the main VCC supply for the device. This feature allows
the output drivers to drive either 3.3V or 2.5V output
levels while the device logic and the output current drive
is always powered from 3.3V. The output drivers also
provide individually programmable edge rates and open
drain capability. A programmable pullup resistor is pro-
vided to tie off unused inputs and a programmable
bus-hold latch is available to hold tristate outputs in their
last valid state until the bus is driven again by some
device.
The ispLSI 5000V Family features 3.3V, non-volatile in-
system programmability for both the logic and the
interconnect structures, providing the means to develop
truly reconfigurable systems. Programming is achieved
through the industry standard IEEE 1149.1-compliant
Boundary Scan interface. Boundary Scan test is also
supported through the same interface.
An enhanced, multiple cell security scheme is provided
that prevents reading of the JEDEC programming file
when secured. After the device has been secured using
this mechanism, the only way to clear the security is to
execute a bulk-erase instruction.
ispLSI 5000V Family Members
The ispLSI 5000V Family ranges from 256 macrocells to
512 macrocells and operates from a 3.3V power supply.
All family members will be available with multiple pack-
age options. The ispLSI 5000V Family device matrix
showing the various bondout options is shown in the table
below.
The interconnect structure (GRP) is very similar to Lattice's
existing ispLSI 1000, 2000 and 3000 families, but with an
enhanced interconnect structure for optimal pin locking
and logic routing. This eliminates the need for registered
I/O cells or an Output Routing Pool.
Table 1. ispLSI 5000VA Family
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參數(shù)描述 |
|---|---|
| ISPLSI5512VA-70LB272 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-70LB388 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-70LB388I | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-70LQ208 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ISPLSI5512VA-770LB272 | 制造商:Lattice Semiconductor Corporation 功能描述: |
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