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參數(shù)資料
| 型號(hào)： | IT80C52TXXX-20:RD |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1 MM HEIGHT, TQFP-44 |
| 文件頁(yè)數(shù)： | 168/238頁(yè) |
| 文件大?。?/td> | 4549K |
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35
8006K–AVR–10/10
ATtiny24/44/84
7.2.1
Limitations
BOD disable functionality has been implemented in the following devices, only:
ATtiny24, revision E, and newer
ATtiny44, revision D, and newer
ATtiny84, revision B, and newer
Revisions are marked on the device package and can be located as follows:
Bottom side of packages 14P3 and 14S1
Top side of package 20M1
7.3
Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 37, pro-
vides a method to reduce power consumption by stopping the clock to individual peripherals.
The current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current
of I/O Modules” on page 185 for examples.
7.4
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
7.4.1
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. See “Analog to Digital Converter” on page 132 for
details on ADC operation.
7.4.2
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep
modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is
set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-
abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode. See “Analog Comparator” on page 129 for details on how to config-
ure the Analog Comparator.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IT80F | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|50V V(DRM)|8A I(T)RMS|TO-220 |
| IT80G | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:TRIAC|50V V(DRM)|8A I(T)RMS|TO-220 |
| IT810B | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Analog IC |
| IT8152FG | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Specification|Errata_v0.1 for it8152fg_v0.3.4 |
| IT8172G | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:RISC Companion Chip|Errata v0.2 for it8172g_v0.6 |
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