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參數(shù)資料
| 型號： | IV80C52XXX-L16R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 1.40 MM HEIGHT, VQFP-44 |
| 文件頁數(shù)： | 195/210頁 |
| 文件大?。?/td> | 5175K |
| 代理商： | IV80C52XXX-L16R |
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85
8048C–AVR–02/12
ATtiny43U
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-
ble on the pin. The port override function is independent of the Waveform Generation mode.
The design of the Output Compare pin logic allows initialization of the OCnx state before the out-
put is enabled. Note that some COMnx[1:0] bit settings are reserved for certain modes of
operation, see “Register Description” on page 92
12.6.1
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COMnx[1:0] bits differently in Normal, CTC, and PWM
modes. For all modes, setting the COMnx[1:0] = 0 tells the Waveform Generator that no action
on the OCnx Register is to be performed on the next Compare Match. For compare output
actions in the non-PWM modes refer to Table 12-2 on page 92. For fast PWM mode, refer to
Table 12-3 on page 92, and for phase correct PWM refer to Table 12-4 on page 93.
A change of the COMnx[1:0] bits state will have effect at the first Compare Match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOCnx strobe bits.
12.7
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGMn[2:0]) and Compare Out-
put mode (COMnx[1:0]) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COMnx[1:0] bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-
PWM modes the COMnx[1:0] bits control whether the output should be set, cleared, or toggled
at a Compare Match (See “Modes of Operation” on page 85).
For detailed timing information refer to Figure 12-8 on page 90, Figure 12-9 on page 90, Figure
90.
12.7.1
Normal Mode
The simplest mode of operation is the Normal mode (WGMn[2:0] = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOVn) will be set in the same
timer clock cycle as the TCNTn becomes zero. The TOVn Flag in this case behaves like a ninth
bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the TOVn Flag, the timer resolution can be increased by software.
There are no special cases to consider in the Normal mode, a new counter value can be written
anytime.
The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-
put Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
12.7.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGMn[2:0] = 2), the OCRnA Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter
value (TCNTn) matches the OCRnA. The OCRnA defines the top value for the counter, hence
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