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參數(shù)資料
| 型號(hào)： | IW4013BN |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | Dual D Flip-Flop High-Voltage Silicon-Gate CMOS |
| 中文描述： | 雙D觸發(fā)器高壓硅柵CMOS |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大?。?/td> | 177K |
| 代理商： | IW4013BN |
IW4013B
22
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200 k
, Input t
r
=t
f
=20 ns)
V
CC
V
Guaranteed Limit
≥
-55
°
C
3.5
8
12
Symbol
Parameter
25
°
C
3.5
8
12
≤
125
°
C
1.75
4
6
Unit
f
max
Maximum Clock Frequency (Figure 1)
5.0
10
15
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figure 1)
5.0
10
15
300
130
90
300
130
90
600
260
180
ns
t
PLH
Maximum Propagation Delay, Set to Q or Reset
to Q (Figure 2)
5.0
10
15
300
130
90
300
130
90
600
260
180
ns
t
PHL
Maximum Propagation Delay, Set to Q or Reset
to Q (Figure 2)
5.0
10
15
400
170
120
400
170
120
800
340
240
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any Output
(Figure 1)
5.0
10
15
200
100
80
200
100
80
400
200
160
ns
C
IN
Maximum Input Capacitance
-
7.5
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200 k
, Input t
r
=t
f
=20 ns)
V
CC
V
Guaranteed Limit
≥
-55
°
C
140
60
40
Symbol
Parameter
25
°
C
140
60
40
≤
125
°
C
280
120
80
Unit
t
w
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
ns
t
w
Minimum Pulse Width, Set or Reset (Figure 2)
5.0
10
15
180
80
50
180
80
50
360
160
100
ns
t
su
Minimum Setup Time, Data to Clock
(Figure 3)
5.0
10
15
40
20
15
40
20
15
80
40
30
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 3)
5.0
10
15
5
5
5
5
5
5
10
10
10
ns
t
r
, t
f
Maximum Input Rise or Fall Time, Clock
(Figure 1)
5.0
10
15
500
30
6
500
30
6
1000
60
12
μ
s
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