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參數(shù)資料
| 型號： | IW4034B |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | 8-STAGE STATIC BIDIRECTIONAL PARALLEL/ SERIAL INPUT/OUTPUT BUS REGISTER |
| 中文描述： | 8級靜態(tài)雙向并行/串行輸入/輸出總線寄存器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 330K |
| 代理商： | IW4034B |
IW4034B
5
TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER OPERATION
“A”
Enable
P/S
A/B
A/S
L
L
L
X
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs
Disabled
L
L
H
X
Serial Mode, Synch. Serial Data Input, “B” Parallel Data Output
L
H
L
L
Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data
Outputs Disabled
L
H
L
H
Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data
Outputs Disabled
L
H
H
L
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data
Outputs, Synch. Data Recirculation
L
H
H
H
Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data
Outputs, Asynch. Data Recirculation
H
L
L
X
Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output
H
L
H
X
Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output
H
H
L
L
Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data
Output
H
H
L
H
Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data
Output
H
H
H
L
Parallel Mode; “A” Synch. Parallel Data Input, “B” Parallel Data
Output
H
H
H
H
Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data
Output
*
Outputs change at positive transition of clock in the serial mode and when the A/S control
input is “l(fā)ow” in the parallel mode. During transfer from parallel to serial operation A/S should
remain low in oder to prevent D
S
transfer into Flip Flops.
X = Don’t Care
PARALLEL OPERATION
A high P/S input signal allows data transfer into the register via the parallel data lines
synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input
is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B
input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B
signal reverses the direction of data flow.
The AE input is an additional feature which allows many registers to feed data to a common
bus. The A DATA lines are enabled only when this signal is high.
Data storage through recirculation of data in each register stage is accomplished by making
the A/B signal high and the AE signal low.
SERIAL OPERATION
A low P/S signal allows serial data to transfer into the register synchronously with the positive
transition of the clock. The A/S input is internally disabled when the register is in the serial mode
(asynchronous serial operation is not allowed).
The serial data appears as output data on either the B lines (when A/B is high) or the A lines
(when A/B is low and the AE signal is high).
Operation
*
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IW4034BDW | 1 RES 15K OHM 1/10W 5% RC0805 |
| IW4034BN | 8-STAGE STATIC BIDIRECTIONAL PARALLEL/ SERIAL INPUT/OUTPUT BUS REGISTER |
| IW4040B | 12-Stage Binary Ripple Counter |
| IW4040BD | .01, 1K54, .125W, 1%, SMD 0805 |
| IW4040BN | 12-Stage Binary Ripple Counter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IW4034BDW | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:8-STAGE STATIC BIDIRECTIONAL PARALLEL/ SERIAL INPUT/OUTPUT BUS REGISTER |
| IW4034BN | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register High-Voltage Silicon-Gate CMOS |
| IW4040B | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS |
| IW4040BD | 制造商:INTEGRAL 制造商全稱:INTEGRAL 功能描述:12-Stage Binary Ripple Counter |
| IW4040BN | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:12-Stage Binary Ripple Counter High-Voltage Silicon-Gate CMOS |
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