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參數(shù)資料
| 型號： | IW4042B |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | QUAD CLOCKED <D> LATCH |
| 中文描述： | 四時(shí)鐘\u003cD\u003e鎖存 |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 154K |
| 代理商： | IW4042B |
IW4042B
1
Q
UAD
C
LOCKED
D
L
ATCH
High-Voltage Silicon-Gate CMOS
CD4042B types contain four latch circuits, each strobed by a
common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p-channel output
devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
providing the CLOCK and POLARITY levels defined above are
present. When a CLOCK transition occurs (positive for
POLARITY = 0 and negative for POLARTY = 1) the information
present at the input during the CLOCK transition is retained at
the outputs until an opposite CLOCK transition occurs.
The CD4042B types are supplied in 16-lead hermetic dual-in-
line ceramic packages (D and F suffixes); 16-lead dual-in-line
plastic package (E suffix), and in chip form (H suffix).
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1
μ
A at 18 V over full package-
temperature range; 100 nA at 18 V and 25
°
C
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4042BN Plastic
IW4042BD SOIC
T
A
= -55
°
to 125
°
C for all
packages
PIN ASSIGNMENT
1
2
3
5
4
6
7
8
16
15
14
13
12
11
10
9
GND
VCC
Q1
CLOCK
D1
POLARITY
D2
D4
Q4
D3
Q3
Q3
Q2
Q2
Q4
Q1
FUNCTION TABLE
Inputs
Clock
Polarity
0
1
1
0
Outputs
Q
D
Latch
D
Latch
0
0
1
1
LOGIC DIAGRAM
PIN 16 =V
CC
PIN 8 = GND
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IW4042BD | QUAD CLOCKED <D> LATCH |
| IW4042BN | QUAD CLOCKED <D> LATCH |
| IW4093B | Quad 2-Input NAND Schmitt Triggers High-Voltage Silicon-Gate CMOS |
| IW4093BD | Quad 2-Input NAND Schmitt Triggers High-Voltage Silicon-Gate CMOS |
| IW4093BN | Quad 2-Input NAND Schmitt Triggers High-Voltage Silicon-Gate CMOS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IW4042BD | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Quad Clocked ??Latch High-Voltage Silicon-Gate CMOS |
| IW4042BN | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Quad Clocked ??Latch High-Voltage Silicon-Gate CMOS |
| IW4043B | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS |
| IW4043BD | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS |
| IW4043BN | 制造商:IKSEMICON 制造商全稱:IK Semicon Co., Ltd 功能描述:Quad 3-State R/S Latches High-Voltage Silicon-Gate CMOS |
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