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參數(shù)資料
| 型號(hào)： | IW4042BN |
| 廠商： | INTEGRAL JOINT STOCK COMPANY |
| 英文描述： | QUAD CLOCKED <D> LATCH |
| 中文描述： | 四時(shí)鐘\u003cD\u003e鎖存 |
| 文件頁(yè)數(shù)： | 4/5頁(yè) |
| 文件大小： | 154K |
| 代理商： | IW4042BN |
IW4042B
4
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200 k
, Input t
r
=t
f
=20 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
≥
-55
°
C
450
200
160
160
500
230
180
180
220
110
80
80
300
150
100
100
200
100
80
80
7.5
25
°
C
≤
125
°
C
900
400
320
1000
460
360
440
220
160
600
300
200
400
200
160
Unit
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to
Q (Figure 1)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
-
450
200
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to
Q (Figure 1)
500
230
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Data to Q
(Figure 2)
220
110
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Data to Q
(Figure 2)
300
150
ns
t
TLH
, t
THL
Maximum Output Transition Time, Any
Output (Figure 1)
200
100
ns
C
IN
Maximum Input Capacitance
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200 k
, Input t
r
=t
f
=20 ns)
Symbol
Parameter
V
CC
V
Guaranteed Limit
≥
-
55
°
C
200
100
60
60
50
30
25
25
120
60
50
50
Not rise or fall
time sensitive
25
°
C
≤
125
°
C
400
200
120
100
60
50
240
120
100
Unit
t
w
Minimum Pulse Width, Clock (Figure 1)
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
200
100
ns
t
su
Minimum Setup Time, Data to Clock
(Figure 1)
50
30
ns
t
h
Minimum Hold Time, Clock to Data
(Figure 1)
120
60
ns
t
r
, t
f
Maximum Input Rise or Fall Time,
Clock (Figure 1)
μ
s
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