參數(shù)資料
型號: IW4093BD
廠商: INTEGRAL JOINT STOCK COMPANY
英文描述: Quad 2-Input NAND Schmitt Triggers High-Voltage Silicon-Gate CMOS
中文描述: 四2輸入與非施密特觸發(fā)器高壓硅柵CMOS
文件頁數(shù): 3/5頁
文件大?。?/td> 134K
代理商: IW4093BD
IW4093B
144
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
-55
°
C
Symbol
Parameter
Test Conditions
25
°
C
125
°
C
2.2
4.6
6.8
Unit
V
T
+min
Minimum Positive-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
5.0
10
15
2.2
4.6
6.8
2.2
4.6
6.8
V
Input on terminals A and B;
other inputs to V
CC
5.0
10
15
2.6
5.6
6.3
2.6
5.6
6.3
2.6
5.6
6.3
V
T
+max
Maximum Positive-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
5.0
10
15
3.6
7.1
10.8
3.6
7.1
10.8
3.6
7.1
10.8
V
Input on terminals A and B;
other inputs to V
CC
5.0
10
15
4
8.2
12.7
4
8.2
12.7
4
8.2
12.7
V
T
-min
Minimum Negative-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
5.0
10
15
0.9
2.5
4
0.9
2.5
4
0.9
2.5
4
V
Input on terminals A and B;
other inputs to V
CC
5.0
10
15
1.4
3.4
4.8
1.4
3.4
4.8
1.4
3.4
4.8
V
T
-max
Maximum Negative-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
5.0
10
15
2.8
5.2
7.4
2.8
5.2
7.4
2.8
5.2
7.4
V
Input on terminals A and B;
other inputs to V
CC
5.0
10
15
3.2
6.6
9.6
3.2
6.6
9.6
3.2
6.6
9.6
V
H
min
Note
Minimum Hysteresis
Voltage
Input on terminals A or B;
other inputs to V
CC
5.0
10
15
0.3
1.2
1.6
0.3
1.2
1.6
0.3
1.2
1.6
V
Input on terminals A and B;
other inputs to V
CC
5.0
10
15
0.3
1.2
1.6
0.3
1.2
1.6
0.3
1.2
1.6
V
H
max
Note
Maximum Hysteresis
Voltage
Input on terminals A or B;
other inputs to V
CC
5.0
10
15
1.6
3.4
5
1.6
3.4
5
1.6
3.4
5
V
Input on terminals A and B;
other inputs to V
CC
5.0
10
15
1.6
3.4
5
±
0.1
1.6
3.4
5
±
0.1
1.6
3.4
5
±
1.0
I
IN
Maximum Input
Leakage Current
V
IN
= GND or V
CC
18
μ
A
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