參數(shù)資料
型號: JANTXV2N6849U
英文描述: -100V Single P-Channel Hi-Rel MOSFET in a 18-pin LCC package
中文描述: - 100V的單P溝道高可靠性的18 MOSFET的引腳LCC封裝
文件頁數(shù): 19/21頁
文件大?。?/td> 137K
代理商: JANTXV2N6849U
MIL-PRF-19500/368F
7
Dimensions
Symbol
Inches
Millimeters
Note
Min
Max
Min
Max
A
.061
.075
1.55
1.90
3
A1
.029
.041
0.74
1.04
B1
.022
.028
0.56
0.71
B2
.075 REF
1.91 REF
B3
.006
.022
0.15
0.56
5
D
.145
.155
3.68
3.93
D1
.045
.055
1.14
1.39
D2
.0375 BSC
.952 BSC
D3
.155
3.93
E
.215
.225
5.46
5.71
E3
.225
5.71
L1
.032
.048
0.81
1.22
L2
.072
.088
1.83
2.23
L3
.003
.007
0.08
0.18
5
NOTES:
1. Dimensions are in inches.
2. Metric equivalents are given for general information only.
3. Dimension "A" controls the overall package thickness. When a window lid is used, dimension "A" must
increase by a minimum of .010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).
4. The corner shape (square, notch, radius, etc.) may vary at the manufacturer's option, from that shown on the
drawing.
5. Dimensions "B3" minimum and "L3" minimum and the appropriately castellation length define an unobstructed
three-dimensional space traversing all of the ceramic layers in which a castellation was designed.
(Castellations are required on bottom two layers, optional on top ceramic layer.) Dimension "B3" maximum
and "L3" maximum define the maximum width and depth of the castellation at any point on its surface.
Measurement of these dimensions may be made prior to solder dipping.
* FIGURE 4. Physical dimensions, surface mount (2N3439UA, 2N3440UA) version.
相關(guān)PDF資料
PDF描述
JANTXV2N6851U -200V Single P-Channel Hi-Rel MOSFET in a 18-pin LCC package
JANTXV2N6896 TRANSISTOR | MOSFET | P-CHANNEL | 100V V(BR)DSS | 6A I(D) | TO-204AA
JANTXV2N6898 TRANSISTOR | MOSFET | P-CHANNEL | 100V V(BR)DSS | 25A I(D) | TO-204AE
JANTXV2N6902 TRANSISTOR | MOSFET | N-CHANNEL | 100V V(BR)DSS | 12A I(D) | TO-204AA
JANTXV2N6904 TRANSISTOR | MOSFET | N-CHANNEL | 200V V(BR)DSS | 8A I(D) | TO-204AA
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