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參數(shù)資料
| 型號： | JM4020ABEA |
| 元件分類： | 通用總線功能 |
| 英文描述： | COUNTER|UP|14-BIT BINARY|CMOS|DIP|16PIN|CERAMIC |
| 中文描述： | 柜臺前排隊| 14 |位二進(jìn)制|的CMOS |雙酯| 16PIN |陶瓷 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 20K |
| 代理商： | JM4020ABEA |
MJCD4020A-X REV 1A0
MICROCIRCUIT DATA SHEET
(Continued)
Note 6:
Sample tested (Method 5005, Table 1) on each MFG. lot at +25C temperature only,
subgroup A1.
Screen tested 100% on each device at +25C temperature only, subgroup A9.
Sample tested (Method 5005, Table 1) on each MFG. lot at +25C, +125C and -55C
temperature, subgroups A9, 10 and 11.
VIL, VIH, IOL and IOH are guaranteed by applying specified conditions and testing VOL
and VOH.
Note 10: Guaranteed parameter. This test is only performed during initial qualification or
after changes to either design or process which may impact capacitance.
Note 11: Guaranteed parameter, not tested.
Note 12: Drift values need not be calculated if post burn-in electrical test is performed
within 24 hours after burn-in.
Note 13: Screen tested 100% on each device at +25C temperature only, subgroup 7. "L" is
defined as VSS + 0.5V and "H" is defined as VDD - 0.5V.
Note 14: Sample tested (Method 5005, Table 1) on each MFG. lot at +25C temperature only,
subgroup 7. "L" is defined as VSS + 0.5V and "H" is defined as VDD - 0.5V.
Note 7:
Note 8:
Note 9:
7
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