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參數(shù)資料
| 型號： | K4D28163HD-TC40 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit DDR SDRAM |
| 中文描述： | 128Mbit DDR SDRAM的 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 121K |
| 代理商： | K4D28163HD-TC40 |
128M DDR SDRAM
K4D28163HD
- 8 -
Rev. 1.4(Aug. 2002)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency,
addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for
variety of different applications. The default value of the mode register is not defined, therefore the mode register must be
written after EMRS setting for proper operation. The mode register is written by asserting low on CS, RAS, CAS and
WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of
address pins A
0
~ A
11
and BA
0
, BA
1
in the same cycle as CS, RAS, CAS and WE going low is written in the mode register.
Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents
can be changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state. The mode register is divided into various fields depending on functionality. The burst length uses A
0
~ A
2
,
addressing mode uses A
3
, CAS latency(read latency from column address) uses A
4
~ A
6
. A
7
is used for test mode. A
8
is
used for DLL reset. A
7,
A
8
, BA
0
and BA
1
must be set to low for normal MRS operation. Refer to the table for specific codes
for various burst length, addressing modes and CAS latencies.
MODE REGISTER SET(MRS)
Address Bus
Mode Register
CAS Latency
A
6
A
5
A
4
Latency
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Burst Length
A
2
A
1
A
0
Burst Type
Sequential
Interleave
0
0
0
Reserve
Reserve
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserve
Reserve
1
0
1
Reserve
Reserve
1
1
0
Reserve
Reserve
1
1
1
Reserve
Reserve
Burst Type
A
3
Type
0
Sequential
1
Interleave
* RFU(Reserved for future use)
should stay "0" during MRS
cycle.
MRS Cycle
Command
*1 : MRS can be issued only at all banks precharge state.
*2 : Minimum
t
RP
is required to issue MRS command.
CK, CK
Precharge
All Banks
NOP
NOP
MRS
NOP
NOP
2
0
1
5
3
4
8
6
7
Any
NOP
Command
t
RP
t
MRD
=2 t
CK
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
RFU
0
RFU
DLL
TM
CAS Latency
BT
Burst Length
BA
0
A
n
~ A
0
0
MRS
1
EMRS
DLL
A
8
DLL Reset
0
No
1
Yes
Test Mode
A
7
mode
0
Normal
1
Test
NOP
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| K4D310-AB20-09 | 功能描述:鼓風(fēng)機 AC CENTRIF BLOWER RoHS:否 制造商:Murata 產(chǎn)品:Blowers 電流類型:DC 電源電壓:5.3 V 氣流:1 l/min 軸承類型: 噪聲: 速度: 功率額定值: 框架尺寸 (mm):20 mm x 20 mm x 1.85 mm 外殼材料: 端接類型:SMD/SMT 系列:MZB |
| K4D450-AH09-05 | 功能描述:鼓風(fēng)機 AC CENTRIF BLOWER RoHS:否 制造商:Murata 產(chǎn)品:Blowers 電流類型:DC 電源電壓:5.3 V 氣流:1 l/min 軸承類型: 噪聲: 速度: 功率額定值: 框架尺寸 (mm):20 mm x 20 mm x 1.85 mm 外殼材料: 端接類型:SMD/SMT 系列:MZB |
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