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參數(shù)資料
| 型號： | K4D28163HD-TC50 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 128Mbit DDR SDRAM |
| 中文描述： | 128Mbit DDR SDRAM的 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 121K |
| 代理商： | K4D28163HD-TC50 |
128M DDR SDRAM
K4D28163HD
- 13 -
Rev. 1.4(Aug. 2002)
AC CHARACTERISTICS
Parameter
Sym-
bol
t
CK
t
CH
t
CL
t
DQSCK
t
AC
-36
-40
-50
-60
Unit Note
Min
3.6
0.45
Max
6
0.55
Min
4.0
0.45
Max
7
0.55
Min
5.0
0.45
Max
10
0.55
Min
6.0
0.45
Max
10
0.55
CK cycle time
CK high level width
CL=3
ns
tCK
CK low level width
DQS out access time from CK
0.45
-0.6
0.55
0.6
0.45
-0.6
0.55
0.6
0.45
-0.7
0.55
0.7
0.45
-0.75
0.55
0.75
tCK
ns
Output access time from CK
Data strobe edge to Dout edge
t
DQSQ
Read preamble
-0.6
0.6
-0.6
0.6
-0.7
0.7
-0.75
0.75
ns
-
0.4
1.1
-
0.4
1.1
-
0.45
1.1
-
0.5
1.1
ns
tCK
1
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
0.9
0.9
0.9
0.9
Read postamble
CK to valid DQS-in
0.4
0.85
0.6
1.15
0.4
0.85
0.6
1.15
0.4
0.8
0.6
1.2
0.4
0.75
0.6
1.25
tCK
tCK
DQS-In setup time
0
-
0
-
0
-
0
-
ns
DQS-in hold time
DQS write postamble
0.35
0.4
-
0.35
0.4
-
0.3
0.4
-
0.25
0.4
-
tCK
tCK
0.6
0.6
0.6
0.6
DQS-In high level width
DQS-In low level width
Address and Control input setup
t
IS
0.4
0.4
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
0.6
0.6
0.4
0.4
0.6
0.6
tCK
tCK
0.9
-
0.9
-
1.0
-
1.1
-
ns
Address and Control input hold
DQ and DM setup time to DQS
t
IH
t
DS
t
DH
0.9
0.4
-
-
0.9
0.4
-
-
1.0
0.45
-
-
1.1
0.5
-
-
ns
ns
DQ and DM hold time to DQS
0.4
-
0.4
-
0.45
tCLmin
or
tCHmin
tHP-0.45
-
0.5
-
ns
Clock half period
t
HP
tCLmin
or
tCHmin
tHP-0.4
-
tCLmin
or
tCHmin
tHP-0.4
-
-
tCLmin
or
tCHmin
tHP-0.5
-
ns
1
Data output hold time from DQS
t
QH
-
-
-
-
ns
1
Note 1 :
- The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
case
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
- tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
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| K4D28163HD-TC60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mbit DDR SDRAM |
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