參數(shù)資料
型號： K4D551638D-TC50
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 256Mbit GDDR SDRAM
中文描述： 片256Mbit GDDR SDRAM內(nèi)存
文件頁數(shù)： 13/18頁
文件大?。?/td> 230K
代理商： K4D551638D-TC50
256M GDDR SDRAM
K4D551638D-TC
- 13 -
Rev 1.8 (Oct. 2003)
AC CHARACTERISTICS
Parameter
Symbol
-2A
-33
-36
-40
-45
Unit
Note
Min
-
2.86
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Max
Min
-
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.35
0.35
tCLmin
or
tCHmin
tHP-
0.35
Max
Min
-
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-
0.4
Max
Min
-
4.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
tHP-
0.4
Max
Min
4.5
-
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.45
0.45
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-
0.45
Max
CK cycle time
CL=3
CL=4
tCK
10
10
10
10
10
ns
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
CK high level width
CK low level width
DQS out access time from CK
Output access time from CK
Data strobe edge to Dout edge
Read preamble
Read postamble
CK to valid DQS-in
DQS-In setup time
DQS-in hold time
DQS write postamble
DQS-In high level width
DQS-In low level width
Address and Control input setup
Address and Control input hold
DQ and DM setup time to DQS
DQ and DM hold time to DQS
tCH
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPREH
tWPST
tDQSH
tDQSL
tIS
tIH
tDS
tDH
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.35
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
-
0.6
0.55
0.55
-
-
-
-
1
Clock half period
tHP
-
-
-
-
-
ns
1
Data output hold time from DQS
tQH
-
-
-
-
-
ns
1
AC CHARACTERISTICS (I)
Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM
Parameter
Symbol
-2A
-33
-36
-40
-45
Unit
Note
Min
15
17
10
5
Max
-
-
100K
-
Min
15
17
10
5
Max
-
-
100K
-
Min
15
17
10
5
Max
-
-
100K
-
Min
13
15
9
4
Max
-
-
100K
-
Min
12
14
8
4
Max
-
-
100K
-
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay for Read
tRC
tRFC
tRAS
tRCDRD
tRCDW
tCK
tCK
tCK
tCK
RAS to CAS delay for Write
3
-
3
-
3
-
2
-
2
-
tCK
Row precharge time
Row active to Row active
Last data in to Row precharge
@Normal Precharge
Last data in to Row precharge
@Auto Precharge
Last data in to Read command
Col. address to Col. address
Mode register set cycle time
Auto precharge write recovery +
Precharge
Exit self refresh to read command tXSR
tRP
tRRD
5
3
-
-
5
3
-
-
5
3
-
-
4
3
-
-
4
3
-
-
tCK
tCK
tWR
3
-
3
-
3
-
3
-
3
-
tCK
1
tWR_A
3
-
3
-
3
-
3
-
3
-
tCK
1
tCDLR
tCCD
tMRD
3
1
2
-
-
-
3
1
2
-
-
-
2
1
2
-
-
-
2
1
2
-
-
-
2
1
2
-
-
-
tCK
tCK
tCK
1
tDAL
8
-
8
-
8
-
7
-
7
-
tCK
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
200
3tCK
+tIS
7.8
-
tCK
Power down exit time
tPDEX
-
-
-
-
-
ns
Refresh interval time
tREF
-
-
-
-
-
us
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