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參數(shù)資料
| 型號(hào)： | K4D551638D-TC60 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit GDDR SDRAM |
| 中文描述： | 片256Mbit GDDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 230K |
| 代理商： | K4D551638D-TC60 |
256M GDDR SDRAM
K4D551638D-TC
4M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM
with Bi-directional Data Strobe and DLL
- 3 -
Rev 1.8 (Oct. 2003)
The K4D551638D is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by
16 bits, fabricated with SAMSUNG
’
s high performance CMOS technology. Synchronous features with Data Strobe allow
extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety
of high performance memory system applications.
GENERAL DESCRIPTION
FOR 4M x 16Bit x 4 Bank DDR SDRAM
FEATURES
ORDERING INFORMATION
1. For the K4D551638D-TC2A, VDD & VDDQ = 2.8V+0.1V
2. For the K4D551638D-TC60, VDD & VDDQ = 2.5V+5%.
3. K4D551638D-LC is the Lead free package part number
Part NO.
Max Freq.
Max Data Rate
Interface
Package
K4D551638D-TC2A
*
350MHz
700Mbps/pin
SSTL_2
66pin TSOP-II
K4D551638D-TC33
300MHz
600Mbps/pin
K4D551638D-TC36
275MHz
550Mbps/pin
K4D551638D-TC40
250MHz
500Mbps/pin
K4D551638D-TC45
222MHz
444Mbps/pin
K4D551638D-TC50
200MHz
400Mbps/pin
K4D551638D-TC60
*
166MHz
333Mbps/pin
2.6V + 0.1V power supply for device operation
2.6V + 0.1V power supply for I/O interface
SSTL_2 compatible inputs/outputs
4 banks operation
MRS cycle with address key programs
-. Read latency 3, 4 (clock)
-. Burst length (2, 4 and 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive
going edge of the system clock
Differential clock input
No Wrtie-Interrupted by Read Function
2 DQS’s ( 1DQS / Byte )
Data I/O transactions on both edges of Data strobe
DLL aligns DQ and DQS transitions with Clock transition
Edge aligned data & data strobe output
Center aligned data & data strobe input
DM for write masking only
Auto & Self refresh
32ms refresh period (4K cycle) for -TC2A/33/36/40/45
64ms refresh period (8K cycle) for -TC50/60
66pin TSOP-II
Maximum clock frequency up to 350MHz
Maximum data rate up to 700Mbps/pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K4D623238B-GC | 64Mbit DDR SDRAM |
| K4D64163HF | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC33 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC36 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| K4D64163HF-TC40 | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K4D551638F-LC40000 | 制造商:Samsung 功能描述:DDR SGRAM X16 TSOP2 - Trays 制造商:Samsung Semiconductor 功能描述:DRAM Chip GDDR SDRAM 256M-Bit 16Mx16 2.6V 66-Pin TSOP-II |
| K4D551638F-TC | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638F-TC33 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638F-TC36 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
| K4D551638F-TC40 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mbit GDDR SDRAM |
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