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參數資料
| 型號： | K4D64163HF-TC50 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM |
| 中文描述： | 100萬× 16 × 4，銀行雙數據速率同步DRAM |
| 文件頁數： | 13/16頁 |
| 文件大?。?/td> | 162K |
| 代理商： | K4D64163HF-TC50 |
64M DDR SDRAM
K4D64163HF
- 13 -
Rev. 1.1(Aug. 2002)
C CHARACTERISTICS
Parameter
Sym-
bol
t
CK
t
CH
t
CL
t
DQSCK
t
AC
-33
-36
-40
-50
-60
Unit Note
Min
3.3
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.8
0
0.45
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
Max
4.0
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.25
-
-
0.6
0.6
0.6
-
-
-
-
Min
3.6
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
Max
6
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
Min
4.0
0.45
0.45
-0.6
-0.6
-
0.9
0.4
0.85
0
0.35
0.4
0.4
0.4
0.9
0.9
0.4
0.4
tCLmin
or
tCHmin
Max
7
0.55
0.55
0.6
0.6
0.4
1.1
0.6
1.15
-
-
0.6
0.6
0.6
-
-
-
-
Min
5.0
0.45
0.45
-0.7
-0.7
-
0.9
0.4
0.8
0
0.3
0.4
0.4
0.4
1.0
1.0
0.45
0.45
tCLmin
or
tCHmin
tHP-
0.45
Max
10
0.55
0.55
0.7
0.7
0.45
1.1
0.6
1.2
-
-
0.6
0.6
0.6
-
-
-
-
Min
6.0
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.4
0.4
0.4
1.1
1.1
0.5
0.5
tCLmin
or
tCHmin
Max
10
0.55
0.55
0.75
0.75
0.5
1.1
0.6
1.25
-
-
0.6
0.6
0.6
-
-
-
-
K cycle time
K high level width
K low level width
QS out access time from CK
utput access time from CK
ata strobe edge to Dout edge
t
DQSQ
ead preamble
ead postamble
K to valid DQS-in
QS-In setup time
QS-in hold time
QS write postamble
QS-In high level width
QS-In low level width
ddress and Control input setup
t
IS
ddress and Control input hold
t
IH
Q and DM setup time to DQS
t
DS
Q and DM hold time to DQS
CL=3
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
ns
ns
ns
ns
1
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
t
DH
lock half period
t
HP
-
-
-
-
-
ns
1
ata output hold time from DQS
t
QH
tHP-0.4
tHP-0.4
-
tHP-0.4
-
-
tHP-0.5
-
ns
1
ote 1 :
The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data
strobe and all data associated with that data strobe are coincidentally valid.
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst
ase
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
variation and replaces tDV
tQHmin = tHP-X where
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
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