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    參數(shù)資料
    型號(hào): K4H1G3238D-TCA2
    廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
    英文描述: 128Mb DDR SDRAM
    中文描述: 128MB DDR SDRAM的
    文件頁(yè)數(shù): 28/53頁(yè)
    文件大小: 669K
    代理商: K4H1G3238D-TCA2
    - 28 -
    REV. 1.0 November. 2. 2000
    128Mb DDR SDRAM
    3.3.10 DM masking
    The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle, not read
    cycle. When the data mask is activated (DM high) during write operation, DDR SDRAM does not accept the
    corresponding data.(DM to data-mask latency is zero).
    DM must be issued at the rising or falling edge of data strobe.
    Command
    < Burst Length=8 >
    WRITE
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    NOP
    DQS
    DQ
    s
    Din 0
    Din 1
    Din 2
    Din 3
    t
    DQSS
    DM
    Din 4
    Din 5
    Din 6
    Din7
    masked by DM=H
    2
    0
    1
    5
    3
    4
    8
    6
    7
    CK
    CK
    6. When terminating a burst Read command, the BST command must be issued L
    BST
    (“BST Latency”) clock
    cycles before the clock edge at which the output buffers are tristated, where L
    BST
    equals the CAS latency
    for read operations. This is shown in previous page Figure with examples for CAS latency (CL) of 1.5, 2,
    2.5, 3 and 3.5 (only selected CAS latencies are required by the DDR SDRAM standards, the others are
    optional).
    7. When the burst terminates, the DQ and DQS pins are tristated.
    The BST command is not byte controllable and applies to all bits in the DQ data word and the(all) DQS pin(s).
    Figure 18. DM masking timing
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