參數(shù)資料
型號(hào)： K4H510438C-UCB3
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mb C-die DDR SDRAM Specification
中文描述： 葷的512Mb芯片DDR SDRAM內(nèi)存規(guī)格
文件頁(yè)數(shù)： 16/24頁(yè)
文件大?。?/td> 367K
代理商： K4H510438C-UCB3
Rev. 1.1 June. 2005
DDR SDRAM
DDR SDRAM 512Mb C-die (x4, x8, x16)
Parameter
Symbol
CC
(DDR400@CL=3.0)
Min
55
70
40
15
15
10
15
2
-
6
5
0.45
0.45
-0.55
-0.65
-
0.9
0.4
0.72
0
0.25
0.2
0.2
0.35
0.35
0.6
0.6
B3
(DDR333@CL=2.5)
Min
60
72
42
18
18
12
15
1
7.5
6
-
0.45
0.45
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
A2
(DDR266@CL=2.0)
Min
65
75
45
20
20
15
15
1
7.5
7.5
-
0.45
0.45
-0.75
-0.75
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
B0
(DDR266@CL=2.5) Unit
Min
Max
65
75
45
70K
20
20
15
15
1
10
7.5
-
0.45
0.55
0.45
0.55
-0.75
+0.75
-0.75
+0.75
-
0.9
0.4
0.75
1.25
0
0.25
0.2
0.2
0.35
0.35
0.9
0.9
Note
Max
Max
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
70K
70K
70K
Clock cycle time
CL=2.0
CL=2.5
CL=3.0
tCK
-
12
12
-
0.55
0.55
+0.6
+0.7
0.45
1.1
0.6
1.25
12
12
-
0.55
0.55
+0.75
+0.75
0.5
1.1
0.6
1.25
12
12
-
12
10
0.55
0.55
+0.55
+0.65
0.4
1.1
0.6
1.28
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup
tCH
tCL
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
tIH
0.5
1.1
0.6
22
13
15, 17~19
15, 17~19
tIS
0.7
0.8
1.0
1.0
ns
16~19
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Mode register set cycle time
DQ & DM setup time to DQS
tIH
tHZ
tLZ
tMRD
tDS
0.7
-0.65
-0.65
10
0.4
0.8
-0.7
-0.7
12
0.45
1.0
-0.75
-0.75
15
0.5
1.0
-0.75
-0.75
15
0.5
ns
ns
ns
ns
ns
ns
16~19
11
11
+0.65
+0.65
+0.7
+0.7
+0.75
+0.75
+0.75
+0.75
j, k
DQ & DM hold time to DQS
tDH
0.4
0.45
0.5
0.5
j, k
Control & Address input pulse width
DQ & DM input pulse width
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
tIPW
tDIPW
tXSNR
tXSRD
tREFI
2.2
1.75
75
200
2.2
1.75
75
200
2.2
1.75
75
200
2.2
1.75
75
200
ns
ns
ns
tCK
us
18
18
7.8
7.8
7.8
7.8
14
Output DQS valid window
tQH
tHP
-tQHS
tCLmin
or tCHmin
-
tHP
-tQHS
tCLmin
or tCHmin
-
tHP
-tQHS
tCLmin
or tCHmin
-
tHP
-tQHS
tCLmin
or tCHmin
-
ns
21
Clock half period
tHP
-
-
-
-
ns
20, 21
Data hold skew factor
DQS write postamble time
Active to Read with Auto precharge
command
tQHS
tWPST
0.5
0.6
0.55
0.6
0.75
0.6
0.75
0.6
ns
tCK
21
12
0.4
0.4
0.4
0.4
tRAP
15
18
20
20
Autoprecharge write recovery +
Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK)
tCK
23
19.0 AC Timming Parameters & Specifications
相關(guān)PDF資料
PDF描述
K4H510438 512Mb B-die DDR SDRAM Specification
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