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參數資料
| 型號： | K4H560838E-GLA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DIODE ZENER TRIPLE ISOLATED 200mW 32.97Vz 5mA-Izt 0.02503 0.05uA-Ir 27 SOT-363 3K/REEL |
| 中文描述： | 256Mb的電子芯片DDR SDRAM內存規(guī)格60Ball FBGA封裝（x4/x8） |
| 文件頁數： | 12/19頁 |
| 文件大?。?/td> | 171K |
| 代理商： | K4H560838E-GLA2 |
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.
Iout = 0mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N N R0 N N N N P0 N N
Read : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
IDD7A : Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.
Iout = 1mA
2. Timing patterns
- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCK
Setup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N
Read : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing
*50% of data changing at every transfer
Legend : A = Activate, R=Read, W=Write, P=Precharge, N=NOP
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相關代理商/技術參數 |
參數描述 |
|---|---|
| K4H560838E-GLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8) |
| K4H560838E-GLB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 60Ball FBGA (x4/x8) |
| K4H560838E-NC/LA2 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560838E-NC/LB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
| K4H560838E-NC/LB3 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256Mb E-die DDR SDRAM Specification 54pin sTSOP(II) |
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